I just came across this graph in the ADS1246/7/8 datasheet (24 bit SD ADC) which rather surprised me:
![](https://www.eevblog.com/forum/projects/ads1248-surprising-noise-versus-vin-graph/?action=dlattach;attach=655332)
Noise v input level graphs aren't especially common in ADC datasheets, but I've never seen one that looks quite like this!
The noise level varies dramatically with Vin, between 50nV and 270nV. Typically I would have expected the noise to be relatively flat v Vin, perhaps rising towards the maximum i/p levels where the reference voltage noise starts to become a bigger percentage of the total. (I've seen one where the noise actually reduces at the maximum input, suggesting the reference noise is negligable compared to ADC noise).
Unfortunately there is nothing in the datasheet referencing this graph or how the measurements were taken, other than Vdd and PGA gain shown on the graph itself. In particular it doesn't say if the internal, or an external reference was used and perhaps more importantly how long the noise was measured for at each input level - assuming it was done discretely rather than using an analogue sweep (with unspecified noise bandwidth).
So would you be happy if you'd selected this ADC on the basis of the 70nV rms noise stated in the noise performance table, not having spotted this graph? Note that the noise performance tables published in pretty much all ADC datasheets are with the input shorted (ie. 0V), and there is no reason to doubt the 70nV figure, but given the unusual wild variation with i/p level shouldn't that have been clearly stated somewhere - eg. by referencing this figure 9 as well as the noise tables in the noise specs?
Is this noise characteristic peculiar to this particular ADC (I hope so) or might there be other, similar third-order (or higher) sigma-delta ADCs with similar, noise characteristics but unspecified in the datasheet?
Is the graph simply wrong? It's not uncommon to have nonsense graphs in datasheets.