The are some parts of the ADC that change with input value, that may cause INL errors, e.g. the integration capacitor voltage (DA, leakage / offset causing drift), and the Input resistor self heating (which we now have a method to try and compensate for) below are my thoughts on how me might be able to try and reduce the influence of each, but happy to hear how you where planning it.
I suppose as a silly thought, we could use the DAC heater to instead measure how changes in heating create offsets while using ground as an input to remove any heating
For charge injection, we could likely measure it, have the input mux grounded, so the net current flow is rather low, switch the input, and measure the amount of charge by the known amount of capacitance on one side, and the resistance on the other (essentially an RC to ground) as the 4053 always operates at roughly 0V, this should be fairly consistent for all 3 channels. you then measure the other injection by switching the input off, and then back on, complete the same measurement but subtract the first measurement.
The error current from the op amp - inputs can be directly measured by disconnecting all inputs from the integrator and measuring with the ADC for the direction and magnitude of the offset, you could also perform a normal conversion and measure it that way if the amount was significant enough, this would give the error current that would have to be subtracted from all inputs, You may be able to isolate what factors are causing what by also measuring it by the offset voltage caused over the input resistor with the input grounded. (e.g. 4pA * 100K = 0.4uV), which arguably puts it well under the effects of the op amps input offset, so I guess he will be the dominating factor... guess that becomes a direct measurement of the offset voltage then, convert to a charge per unit time and subtract.
The linearity over the entire integrator range Is fun, technically the EMF effects of U2 from getting warm when the clipping begins should be cancelled by U11, which I assume is an unintended bonus, C11 being a COG really should be as ideal as things get, most spec sheets show almost no difference with temperature or voltage, I suspect there is on this scale, as at this point input resistor heating and the bias of the integrator are taken in to concideration, I suppose a ramp up / ramp down set of tests could be used to try and find any kind of non linearity with the capacitor, going up for X time, then down for Y time crossing the comparitor line should be equal to going up for half X, down for Y and up for half X, I suppose by flipping around the ratio you could determine where any voltage based deviations may sneak in,
The slope amplifier, with as high a Gain as it has, I'm not sure how much of an influence self heating causes, it would be easy enough to measure, just leave it clipped for variable amounts of time to heat the diodes more or less, R12 gets warm and will be changing value unless we spec him low PPM it will offset the low level gain of the slope amp, R13 really only gets heated by the diodes
U13, nothing really gets hot, and the power of all the parts remains pretty stable,, cant speak for how your using the other half currently, but if it was unused, should not be an error source.
I suppose a fun thing about the test points is you could technically measure the ADC's own performance,
Power supply rejection should be OK for all op amps included, but possibly bad on the MUX,
Crosstalk from the digital signals should not be an issue as they are shielded to ground and have resistors to limit there slope.
I would ask what other sources of INL where you thinking?