[solved] JFETs - Determining which is Source and which Drain purely electrically

[Cerebus]

I'm at the 'back of an envelope' stage in designing an automated transistor curve tracer. The basic idea is that you insert a 2 or 3 terminal semiconductor device into a test socket and it goes off and extracts all the relevant parameters for you. The idea was driven by the fact that I need some matched pairs of JFETs and bipolar transistors, and doing the matching by hand is tedious to say the least. One thing lead to another and I realized it was just as easy to build a fully featured curve tracer as it was to build something that would just extract the parameters that I need to match on.

Anyway, step one was to determine how to recognize what type of device had been inserted into the test socket. E.g. JFET or bipolar transistor, n-channel/NPN, p-channel/PNP etc. It turns out this isn't difficult and it's not difficult to figure out which test pin relates to which device pin (collector, base, emitter, gate and so on).

What turns out to be difficult is deciding which pins of a JFET are source and drain. It's easy to determine whether you've got a p-channel or n-channel JFET, which pin is the gate and which two pins are the channel. The problem is that JFETs are pretty agnostic over which pin (out of the 2 channel ends) acts as source and which as drain - in fact some devices are constructed symmetrically and which is the source and which is the drain are purely arbitrary choices. (Offhand I think the J113 fits this bill.)

A similar problem exists for MOSFETs - JFETs are just my starting point in this as (1) I use them more often, (2) MOSFETs are a little trickier as the gate turn on voltage for some MOSFETs exceeds the breakdown voltages on some other MOSFETs which makes a reliable, safe test method a bit more involved and we don't want that complexity clouding the issue for this problem.

Given that you're already determined that (1) you have a JFET, (2) you know the channel type, (3) you know which terminal is the gate and (4) you know which two terminals are the two ends of the channel: for JFETs which aren't strictly symmetrical, what procedure could one follow, purely using electrical testing*, to determine which terminal should be classified as the source and which as the drain?

Let's try and keep this as abstract as possible. That is, discussing it in terms of the device characteristics rather than concrete implementation terms as the former is quite specific, the latter more 'how long is a piece of string'.

* Using the datasheet is either cheating or besides the point here, depending on your point of view.

[dadler]

From the Peak DCA Pro user guide:

Unlike Depletion Mode MOSFETs, JFETs have no insulation layer on the gate. This means that although the input resistance between the gate and source is normally very high (greater than 100M?), the gate current can rise if the semiconductor junction between the gate and source or between the gate and drain become forward biased. This can happen if the gate voltage becomes about 0.6V higher than either the drain or source terminals for N-Channel devices or 0.6V lower than the drain or source for P-Channel devices.

The internal structure of JFETs is essentially symmetrical about the gate terminal, this means that the drain and source terminals are often indistinguishable by the DCA Pro. The JFET type, gate terminal and measured parameters are displayed however.

I have always seen the device show "Symmetrical" for JFETs but perhaps in some cases it can differentiate?

[MrSlack]

I've naughtily substituted drain and source on a few J113's because I wasn't paying attention and there was no performance difference. I'm not sure I care enough to actually use the correct terminals when I think about it. YMMV.

[Cerebus]

Are you sure that there are any JFETs that are asymmetrical?

Anyway, you should go to the source (ha ha) and ask John Hall at Linear Systems.

Yes, the (very old) National, (oldish) Fairchild and (recent) Interfet databooks helpfully classify JFETs by 'process' and have a page or two for each process which includes characteristic data for that process and a diagram of the die. Some are not symmetrical (e.g. Fairchild process 52 (J201 and friends) has three source contacts and two drain contacts so differing parasitics at least) and some are truly symmetrical (e.g. Fairchild process 53 (2N4117 et al) has two contacts, both singular and of identical shape and size, both labelled 'D or S').

It may be that there is no definitive answer to this and the best we can come up with is that all we can do is say, "this channel terminal has less parasitic impedance".

In hindsight, as always, the question is probably better summed up as: Where there is a difference between source and drain terminals on a JFET is there a universally accepted convention as to which terminal is the source and which the drain?

[Cerebus]

I've naughtily substituted drain and source on a few J113's because I wasn't paying attention and there was no performance difference. I'm not sure I care enough to actually use the correct terminals when I think about it. YMMV.

For most purposes I don't really care - a JFET as an analogue switch ought to be agnostic as to which way current is going. A JFET in a differential input stage might care about differing Cgs and Cds parasitics.

It's more the case that if there is a defined right or wrong way to do this I'd like to do it the right way. If there isn't I'd like to know for a fact that there isn't and at the moment I'm ignorant on this point.

[Cerebus]

But wouldn't it make more sense to just ask a JFET designer?

Firstly, I don't happen to know any. Out of my address book I can find you experts on stress corrosion cracking, Mithras and the cult of Sol Invictus in Roman Britain, lactose dehydrogenase as a marker of sertoli cell damage and many other weird, wonderful and obscure subjects but I'm fresh out of semiconductor physicists. Secondly, the point of this forum existing is surely to share knowledge, so if we come up with an answer it'll be here for others to find in the future.

[MrSlack]

Or buy a big bag of JFETs and measure them all...

[Cerebus]

But wouldn't it make more sense to just ask a JFET designer?

Firstly, I don't happen to know any. Out of my address book I can find you experts on stress corrosion cracking, Mithras and the cult of Sol Invictus in Roman Britain, lactose dehydrogenase as a marker of sertoli cell damage and many other weird, wonderful and obscure subjects but I'm fresh out of semiconductor physicists. Secondly, the point of this forum existing is surely to share knowledge, so if we come up with an answer it'll be here for others to find in the future.

As I said, ask John Hall.  When he gives you the answer, you can share it with us.

http://www.linearsystems.com/founder_pres_bio.php

If the collective wisdom here can't come up with an answer I might, but it's a bit presumptuous to chase down a world class expert as a first, second or even third resort. I know some world class experts in other fields and I wouldn't go to them for advice (unless it was over a beer we were already having) until I'd checked the text books, googled it and asked around my peers - we're at the asking around stage here.

[madires]

In case the JFET isn't symmetrical you can measure the capacitance between gate and the two other pins. Gate-Source capacitance should be much smaller than the Gate-Drain capacitance for a n-channel type. I don't know if that also applies to p-channel types or if it's reversed. The capacitance meaurement is a little bit more complicated because you have to bias the FET with DC and do the capacitance measurement with AC.

[Ian.M]

Measure g_m each way round.  If one is significantly higher than the other, you've identified the actual D and S pins.   If its near enough symmetric, then only the datasheet will tell you which is which.

[Cerebus]

Or buy a big bag of JFETs and measure them all...

Hmm, chicken and egg here. The whole point here is to move on with the design of a box for mass testing and I don't want to do mass testing to design the box for mass testing.

If we don't get anywhere useful I will eventually test a big bag (reel) of FETs as I expect to do this anyway to get some matched pairs and perhaps it'll yield some data that can be used to answer the question. But, this assumes that I don't miss some manipulation that is necessary to detect the effect (if any).

[Cerebus]

In case the JFET isn't symmetrical you can measure the capacitance between gate and the two other pins. Gate-Source capacitance should be much smaller than the Gate-Drain capacitance for a n-channel type. I don't know if that also applies to p-channel types or if it's reversed. The capacitance meaurement is a little bit more complicated because you have to bias the FET with DC and do the capacitance measurement with AC.

Yeah, I really want to avoid AC testing if at all possible as it'd more than double the complexity of the instrument and DC measurements are good enough for the vast majority of my purposes.

[Cerebus]

Measure g_m each way round.  If one is significantly higher than the other, you've identified the actual D and S pins.   If its near enough symmetric, then only the datasheet will tell you which is which.

Sigh! It's chuffing obvious now you've said it, and I'm sitting here wondering why the hell it didn't occur to me. Thanks!

It's also galling that I was told this by Ian.M when this Ian M should have realized it for himself!
Ian M(ason)

[dom0]

But wouldn't it make more sense to just ask a JFET designer?

Firstly, I don't happen to know any. Out of my address book I can find you experts on stress corrosion cracking, Mithras and the cult of Sol Invictus in Roman Britain, lactose dehydrogenase as a marker of sertoli cell damage and many other weird, wonderful and obscure subjects but I'm fresh out of semiconductor physicists. Secondly, the point of this forum existing is surely to share knowledge, so if we come up with an answer it'll be here for others to find in the future.

As I said, ask John Hall.  When he gives you the answer, you can share it with us.

http://www.linearsystems.com/founder_pres_bio.php

John Hall died a while ago.

[jh15]

Looking at that link, he really was a Hall Effect.

[T3sl4co1l]

MOS is obvious, for three-terminal devices: source is common to substrate, so you get a diode from S to D.

Four terminal MOSFETs have gate vs. "back gate" (substrate) ambiguity, but that is easily resolved (substrate acts like a JFET gate, since after all, it's a diode junction, not MOS).  Such devices are very old and (as far as I know) exclusive to RF, so may have symmetrical D/S construction.

As long as you're tracing curves: JFETs may exhibit "enhancement" under forward gate bias. Worth checking if there's much difference there, too.  In principle, a JFET is a very "short" UJT, so one should expect a small reduction in channel resistance when the gate is forward-biased (because you're injecting carriers into it).  If one pin (D or S) has a greater length of bulk semiconductor in series between the connection and the active (channel) part, it should be apparent.

Supposedly, GaN FETs exhibit fairly significant forward-bias "enhancement", though this operation is not recommended.  (Do they glow blue when you forward bias them, too?)

In the UJT, the bulk part is far longer than the channel part, and the channel part never pinches off under reverse bias, because it's much larger and not surrounded by the control terminal (which we're now calling the emitter).  Because the bulk part is longer, its resistance is dominant in the circuit, and easily modulated by emitter current; thus, the emitter exhibits negative resistance (a positive current flow leads to reducing incremental resistance), and one can construct a relaxation oscillator quite easily.  (Speed is limited by recombination, so expect a few us "turn-off time".  They aren't magic or anything.. not like tunnel or Gunn diodes, which are almost instantaneous.)

Tim

[MarvinTheMartian]

Looking at that link, he really was a Hall Effect.

I knew he was a smart guy but reading that link made me realise just how brilliant he was!
 

[Cerebus]

MOS is obvious, for three-terminal devices: source is common to substrate, so you get a diode from S to D.

Four terminal MOSFETs have gate vs. "back gate" (substrate) ambiguity, but that is easily resolved (substrate acts like a JFET gate, since after all, it's a diode junction, not MOS).  Such devices are very old and (as far as I know) exclusive to RF, so may have symmetrical D/S construction.

A lot of the RF MOSFETs are designed for closely controlled impedances (think striplines) so probably are highly symmetrical. Not my territory really, I rarely go anywhere even remotely near the black arts of RF.

As long as you're tracing curves: JFETs may exhibit "enhancement" under forward gate bias. Worth checking if there's much difference there, too.  In principle, a JFET is a very "short" UJT, so one should expect a small reduction in channel resistance when the gate is forward-biased (because you're injecting carriers into it).  If one pin (D or S) has a greater length of bulk semiconductor in series between the connection and the active (channel) part, it should be apparent.

Supposedly, GaN FETs exhibit fairly significant forward-bias "enhancement", though this operation is not recommended.  (Do they glow blue when you forward bias them, too?)

In the UJT, the bulk part is far longer than the channel part, and the channel part never pinches off under reverse bias, because it's much larger and not surrounded by the control terminal (which we're now calling the emitter).  Because the bulk part is longer, its resistance is dominant in the circuit, and easily modulated by emitter current; thus, the emitter exhibits negative resistance (a positive current flow leads to reducing incremental resistance), and one can construct a relaxation oscillator quite easily.  (Speed is limited by recombination, so expect a few us "turn-off time".  They aren't magic or anything.. not like tunnel or Gunn diodes, which are almost instantaneous.)

I haven't seen a UJT in the flesh since 1973 and that was in a relaxation oscillator.

[RandallMcRee]

The very useful transistor checkers correctly identify GDS on the JFETs that i tested. You might look into how that is accomplished. I have not looked but pretty sure that there is open source code out there showing how these checkers are programmed to identify all of these various devices.
E.g
https://www.eevblog.com/forum/testgear/$20-lcr-esr-transistor-checker-project/

Randy

[chris_leyson]

Yes, the (very old) National, (oldish) Fairchild and (recent) Interfet databooks helpfully classify JFETs by 'process' and have a page or two for each process which includes characteristic data for that process and a diagram of the die. Some are not symmetrical (e.g. Fairchild process 52 (J201 and friends) has three source contacts and two drain contacts so differing parasitics at least) and some are truly symmetrical (e.g. Fairchild process 53 (2N4117 et al) has two contacts, both singular and of identical shape and size, both labelled 'D or S').

I don't have my Fairchild jfet data book to hand but I thought jfets were mostly asymetric, it would be good to know though. NXP BF245 is symetrical, data sheet says that drain and source are interchangable. When I manage to find a few will have a look on TEK 7CT1N.

[madires]

It depends on the Transistor Tester's firmware.
k-firmware: outputs Drain and Source, but the meaning is that it could be also vice versa for a JFET
m-firmware: either outputs Drain and Source if it detects a difference, or outputs two "x" in case it seems to be symmetrical

The Transistor Tester can't measure Gate-Source and Gate-Drain capacitances in a proper way to determine the pinout.

[Cerebus]

It depends on the Transistor Tester's firmware.
k-firmware: outputs Drain and Source, but the meaning is that it could be also vice versa for a JFET
m-firmware: either outputs Drain and Source if it detects a difference, or outputs two "x" in case it seems to be symmetrical

The Transistor Tester can't measure Gate-Source and Gate-Drain capacitances in a proper way to determine the pinout.

It sounds like you're describing some existing, un-named, transistor tester.

You seem to have missed the very first sentence of this topic: "I'm at the 'back of an envelope' stage in designing an automated transistor curve tracer."

[danadak]

A good resource for in depth questions is the vendor. For example I have
used ON Semi for questions that exceeded the coverage of datasheets. You
can post email questions, some sites now support chat. In those cases
the apps EE contacts the design group.

One caution on broad based testing. Some devices with incredibly small junctions
do not want their gate junction forward biased. Causes damage to the junction.
I recall this, out of my faulty memory, was a JFET problem. Damage was not necessarily
catastrophic, but changed device characteristics.


Regards, Dana.

[rfeecs]

Are you sure that there are any JFETs that are asymmetrical?

Anyway, you should go to the source (ha ha) and ask John Hall at Linear Systems.

Yes, the (very old) National, (oldish) Fairchild and (recent) Interfet databooks helpfully classify JFETs by 'process' and have a page or two for each process which includes characteristic data for that process and a diagram of the die. Some are not symmetrical (e.g. Fairchild process 52 (J201 and friends) has three source contacts and two drain contacts so differing parasitics at least) and some are truly symmetrical (e.g. Fairchild process 53 (2N4117 et al) has two contacts, both singular and of identical shape and size, both labelled 'D or S').

It may be that there is no definitive answer to this and the best we can come up with is that all we can do is say, "this channel terminal has less parasitic impedance".

In hindsight, as always, the question is probably better summed up as: Where there is a difference between source and drain terminals on a JFET is there a universally accepted convention as to which terminal is the source and which the drain?

The Fairchild reference is here:
https://www.fairchildsemi.com/application-notes/AN/AN-6609.pdf
Strangely, this looks like a copy of the National Semiconductor FET databook from 1977.  I guess National owned Fairchild at some point, so that may have something to do with it.

The process 52 layout does have 3 source fingers and 2 drain fingers as you say, but it is really just 4 channels in parallel.  All the DC action is happening in the channels, so DC-wise it is symmetrical.  This is assuming the gate placement is in the center of the channel, not offset towards the source.  The layouts only show the metal and not the diffusions so you can't really tell.

For these very simple old JFETs, I would guess they will all measure as symmetrical.

For power JFETs, people may do fancy things like offsetting the gate toward the source to reduce the source resistance.  They may have a vertical structure.  They may also use a different doping profile on the drain to increase drain-gate breakdown voltage.  They may even have the back diode built in like a MOSFET.  Field plates are another way to increase breakdown voltage.

The same type of thing applies to RF MESFETs and pHEMTs which would measure similar to a JFET.  The higher frequency parts are notoriously difficult to measure DC without getting oscillations.  But it should be obvious to tell which is the source from the package, as the source is almost always grounded.

[Zero999]

For power JFETs, people may do fancy things like offsetting the gate toward the source to reduce the source resistance.  They may have a vertical structure.  They may also use a different doping profile on the drain to increase drain-gate breakdown voltage.  They may even have the back diode built in like a MOSFET.  Field plates are another way to increase breakdown voltage.

I haven't heard of power JFETs until now.

Googling found the datasheet linked below, which shows a diode connected between the drain an source, as in a MOSFET.
http://www.infineon.com/dgdl/Infineon-IJW120R100T1-DS-v02_00-en.pdf?fileId=db3a304341e0aed001420353f03a0e4b