Raspberry Pi RP2350A SMPS - Inductor Polarity

[Xena E]

I can see it would make sense to connect the outside winding layer to the CAP rather than the SWITCH, but that's really a capacitive effect.
Any magnetic effect must be second order as a rod-core will be close to rotationally symmetric in field, unless the shielding ferrite itself is asymmetric ?

An easy check will be to swap one around on a board, and see what actually happens 

It would make a good Dave Video

I'm sure the research has been thoroughly done.

From the PDF:

We found that the regulator performance could be massively improved if the inductor is 'the right way round'.

So, what is the axis of the magnetic field on these inductors?

In the conjunction that the magnetic axis of the inductor is horizontal, the only thing that will effect its magnetic field polarity is the manufacturer's direction of 'winding' reversing the component on the board won't change that.

If OTOH the component creates a vertical field axis, it can be changed simply by reversal.

With this kind of hocus-pocus the RP2350A would be perfect for audiophile projects.

 

Having a manufacturer custom-design an indexable inductor is an end-run around understanding and fixing the real cause.  It also ignores all the lessons hardware design companies learned about supply chains during the pandemic. 

Meh.

Piss poor.

Bad luck on the guys who had to sort it.

Datasheet states "Alternatively, DVDD can be supplied directly from an off-chip power source."

I've got a few RP2350s to play with but none of the special inductors, happy to hear a LDO has been used successfully, and datasheet seems to back it up (though I haven't read enough to know if there are sequencing considerations). Shame I didn't see this thread earlier, I would have asked the RPi guys directly.

I'm sure the membership will be interested in your experiences...

[tszaboo]

An external linear regulator can be used.

I'm surprised that this is not an official solution. You don't even need to think hard to figure out that an LDO is cheaper than the inductor and all the supporting components.

This makes me think there may be issues with this. May be sequencing issues or something like that. Things may appear to work until they start to break.

Hopefully Dangerous prototypes cleared that use with the RP guys.

Well, they are using a crappy 1 cent inductor to do the switcher.
Which is not a critique, I use the same type of inductor if it does the job, and trying to keep the BOM low.
Probably this type: https://abracon.com/Magnetics/power/ASMPL.pdf
The shielding on these inductors is non existent.

I bet you, that a Würth MAPI like 74438343022 (likely a 3.3uH part would be needed) would do the job and wouldn't cause any orientation issues.

[PCB.Wiz]

Probably this type: https://abracon.com/Magnetics/power/ASMPL.pdf
The shielding on these inductors is non existent.

Unlikely to be that one as they state this

LX must be fully shielded, 3.3μH ±20% and with a maximum DC resistance of 250mΩ. Saturation current should be at least 1.5A.

Based on the datasheet info, I'd say it is an interpolation of these two existing part numbers that Abracon already make from Digikey info

AOTA-B201610S4R7MT   IND 4.7UH ±20% 1.3A iSat 1.6A Shielded  235mOhm Max
AOTA-B201610S2R2MT   IND 2.2 µH ±20% 2 A iSat 2.6A  Shielded 74mOhm Max

AOTA-B201608S2R2MT   IND 2.2UH 1.8A iSat 2.3A Shielded  148mOhm Max

[idpromnut]

So after re-reading the design doc a few more times, it looks like the placement of the switching inductor and output capacitor are such that they need to be close to the RP2350.  That close proximity of the inductor to output capacitor is causing some of the magnetic field to couple into the output capacitor which in turn is upsetting the switcher control circuitry in the RP2350 (Page 6 of the Hardware Design with RP2350). They note that "shielded" inductor is not what they expected. I'm still not clear on exactly how the magnetic field is coupling into the capacitor but I'm not a great circuit designer.

[dobsonr741]

I think it refers to RP2040's ADC hiccup, is that right?

Code: [Select]

Someone wrote that they also had ADC nonlinearity issue. Most of all, this issue with converter is also the root of cause for ADC issue...
The RP2040 issue is well explained in https://github.com/raspberrypi/pico-feedback/issues/91

[iMo]

I think it refers to RP2040's ADC hiccup, is that right?

Code: [Select]

Someone wrote that they also had ADC nonlinearity issue. Most of all, this issue with converter is also the root of cause for ADC issue...
The RP2040 issue is well explained in https://github.com/raspberrypi/pico-feedback/issues/91

That had been explained by a guy from rpi company in past - a bug in the sizing of the capacitors in the SAR ADC (they use capacitors instead of resistors in there), not fixable (as it would require complete new set of photo-lithography masks, imho).
Anyhow, as has been discussed in a different thread on the 2350 the only way is to use LDOs for the 3.3V and 1.1V voltages (when you want somehow clean noise background).

PS: it does not matter what kind of inductor you are using, or what "polarity" it has - the switchers operate such they produce rather energetic current flows, with any resistances in the circuit (like the onchip tracks) it will always create ripples.
BTW., big players - like ADI, TI - recommend to use LDOs for filtering the switcher's ripples - a) they will sell one chip more  , b) the modern LDOs have got a pretty good PSRR (like ~90+dB) at those freqs,  thus they filter the ripples better than a, say, second order low pass LC filter (2xLC).

[ArdWar]

Oh come on, there are a lot other MCU having embedded DCDC. STM32WB, LPC55, nRF52 etc. All are robust enough not to trip on itself, all are designed reasonable enough by post regulating the DCDC with internal LDO for the actual VCore etc, all provide easy (and documented) means to bypass or disable it.

[iMo]

Oh come on, there are a lot other MCU having embedded DCDC. STM32WB, LPC55, nRF52 etc. All are robust enough not to trip on itself, all are designed reasonable enough by post regulating the DCDC with internal LDO for the actual VCore etc, all provide easy (and documented) means to bypass or disable it.

I would not compare rpi company with the players like STM or NXP etc.
Btw you may disable the 1.1V switcher in sw..
https://www.eevblog.com/forum/microcontrollers/possible-click-bait-title-the-raspberry-pi-pico-2-now-has-extra-risc-v-cores/msg5604377/#msg5604377

.."click bait title" .. a new eevblog feature ?? 

[MK14]

https://www.eevblog.com/forum/microcontrollers/possible-click-bait-title-the-raspberry-pi-pico-2-now-has-extra-risc-v-cores/msg5604377/#msg5604377

.."click bait title" .. a new eevblog feature ?? 

No, not an EEVBLOG Forum feature, that was me!   

Originally, before news of the RP2350/PICO2 release became public, Eben Upton (the main man, at least in terms of public perception, as regards the Raspberry PI organizations), seemed adamant, that there would be NO RISC-V's, in Raspberry Pi's, anytime soon.

So, I thought it would make a good joke, to start the title, with something on the lines of "possible-click-bait-title".

But, almost immediately after creating the thread.  Remembered, that this forum, does NOT seem to appreciate, my sense of humor.  So, I changed the title, before anyone had time to make posts in that thread.

Unfortunately, as good as the forum software is, in many respects.  It DOES NOT, physically change the web url addresses, to reflect the new (edited) thread title.

Hence the 'funny' url to that thread, you quoted.

[deanclaxton]

I'm working on a board right now with RP2350 on it, and tempted to go straight down the 1.1V LDO route instead of trying to source the recommended inductor and following the layout guides around this.

I imagine I'll just leave VREG_FB and VREG_LX as not connected. VREG_VIN still requires power though for the on-chip power-on-reset circuit so I'll still provide 3.3V there with a 4.7uF cap to VREG_PGND which would be tied to the GND plane. I imagine I could get away with a much smaller cap for the VREG_VIN if thats all its being used for (POR). Then again maybe not (RC?). Probably just go with 4.7uF and be done with it.

Has anyone tested this LDO option as yet?

[phil from seattle]

I'm working on a board right now with RP2350 on it, and tempted to go straight down the 1.1V LDO route instead of trying to source the recommended inductor and following the layout guides around this.

I imagine I'll just leave VREG_FB and VREG_LX as not connected. VREG_VIN still requires power though for the on-chip power-on-reset circuit so I'll still provide 3.3V there with a 4.7uF cap to VREG_PGND which would be tied to the GND plane. I imagine I could get away with a much smaller cap for the VREG_VIN if thats all its being used for (POR). Then again maybe not (RC?). Probably just go with 4.7uF and be done with it.

Has anyone tested this LDO option as yet?

Read the dangerous prototypes blog about their experience.  They use a TI TLV74311 + 2 caps. I'm incorporating this into an RP2350B design.  Haven't yet spun the PCB but getting close.