GaN(FET) is a MOSFET. It works exactly like any other (Si, SiC) MOSFET. Power supplies with it uses the same topologies with any other MOSFET. Any difference is minor (in general sense of things) adjustment for difference in gate voltages, and operating frequencies to exploit its strength.
Actually they aren't -- they are HEMTs. The difference in the nature of the channel is significant ("high electron mobility"), but not actually so important for electrical behavior -- behavior
per area yes, but at the board level we can't know/care about chip density too much. But the gate has direct in-circuit consequences. In particular, the gate is constructed of semiconductor layers, doped in such a way as to impress a built-in electric field making it enhancement mode (when applicable), and, one in-circuit consequence is significant leakage current: up to some mA at rated voltage.
This is also why you don't want to overdrive the gate: either it breaks down catastrophically (I haven't tested..!), or it zeners (in which case you literally cannot overdrive it, the voltage becomes fixed and overcurrent ensues). AFAIK, gate current has deleterious effects, hence the rather low and precise operating limit.
GaN is a wide bandgap material, basically meaning, if you forward-bias the not-gate junction, it conducts, with about as much Vf as band gap; combined with structural reasons, it's actually more like double for the gate, hence the 6V limit for a ~3eV material.
I *think*. That last part is very hand-waved, but there are also a few ways I think to construct them, and it might also be tunneling current instead. Also depending on if it's low voltage (e.g. EPC's eGaN line) or high, and, I haven't studied the fab-level details much (also somewhat hard to find, short of journal articles), or what particular lines are using what particular technology.
Hah actually, this one even gives gate curve... sort of. Fractional mA scale. No absolute maximum Ig though.
https://assets.nexperia.com/documents/data-sheet/GAN190-650FBE.pdfAnyway, gate current mainly means you can't just cap-couple it and expect it to work; a regular CMOS style driver is sufficient, but you'll have a rough time employing certain tricks.
The construction also means there's no body diode (or not that you'd want a GaN PN diode anyway, though the blue/UV emission would be a cool party trick), which means synchronous rectification is almost mandatory.
Having literally no body diode, means it reverts to an asymmetrical JFET behavior: the negative Vds region acts like a source follower, i.e. the V-I curve is simply the gate transfer function, hence the soft curve and no stored charge.
Other differences include avalanche behavior (rather, the complete lack thereof), the generally minuscule die (pitiful SOA / overload capacity / robustness; compare a rocket engine to a diesel engine, it's crazy powerful but one misstep and it explodes catastrophically), and the high speed making even very good layouts an electromagnetic embarrassment, heh.
For what it worth, personally I don't think GaNFETs give that much performance benefit over traditional silicon FETs. It has potential for higher efficiency at smaller size, but you aren't gaining much if you aren't size constrained.
Si is impressively good for what it is. The main things these days are, in high voltage ratings, SJ is king, but SJ contributes a hysteresis loss mechanism that can't be avoided even by use of resonant architectures -- or, it can by slowing down switching edges extraordinarily, but that's not at all practical, and by then, your Fsw is so low (10s kHz?) that it doesn't matter anyway.
It's funny, because resonant Si is so efficient that, comparing to yesteryear's planar MOSFETs -- if you even chose devices big enough to achieve the same conduction loss (and you probably didn't, big dies = $$$), you'd pay just as much in sheer gate drive power, as SJ loses in hysteresis. SJ is an impressive advancement, all in all -- just that it isn't without drawbacks.
(Si below 200V or so, is not SJ; it's probably coming, but for now, they can't make fine enough structures to take advantage of it. So for now, lower voltages are ~free of hysteresis loss. Low voltages also cost less Eoss (drain capacitance/charge energy storage / loss), making hard switching just as acceptable; it's not even that hard to make a, say, RC motor drive with >98% efficiency.)
(Also for the same reason, SiC does not use SJ: basically a 700V SiC MOSFET is the same geometry as a planar 100V Si MOSFET, just fabbed in a different material, and whatever other process adjustments of course. So they also have low hysteresis loss. It's probably coming, but also probably not important until ratings of several kV -- devices that are, at least very dangerous to use for one thing, but also tend to be tightly controlled. There are SiC MOSFETs and IGBTs up to 12kV I think, but good luck finding them actually for sale -- implied: without extensive licensing, NDAs, ITAR, etc.. There aren't many customers for products that high, anyway, so marketing them isn't really needed, not in the usual way anyway.)
GaN is good at two things: high density (the transistors are very small), and high efficiency. Granted, efficiency is in part mandatory, given the limited power dissipation (of the small devices themselves, or of the overall PSU), and also kind of an imperative that, if we're going to spend more on these, it better be worth it. It has fast switching (the speed figure-of-merit is wild, say 2-10 times faster than Si of equivalent ratings), which compounds on density: realize the transistors themselves are but a tiny part of the overall build, and magnetics and capacitors dominate the envelope of a power supply. (And isolation gaps, heh, but that's solvable with another expense: potting.) By kicking Fsw up very high (maybe low MHz even), transformers can be shrunk quite a bit -- mind, not at all proportionally so, it's more like a 2nd to 4th root of the frequency ratio, available materials aren't simply proportionally better, wire losses are harder to control, kind of everything is a little worse -- but, also if we raise frequency like a whopping 10x, we still get a big savings on size. And instead of electrolytics, we use polymers or ceramics, particularly on the output side where much less filtering is required. We can't avoid a bulk cap on the primary side, at least not easily*, so that's going to be electrolytic for a long time, but everything else can be shrunken down. And electrolytics themselves are still improving by tiny increment, year on year.
*I've seen the strategy, to use a poled electret ceramic capacitor (these are a standard/available part, if still rather boutique) with a switching converter, to effectively multiply the capacitance at the input port. Basically, a swing of say 20V (out of 400V average or whatever) is magnified to 100 or 200V of swing at the ceramic capacitor, right in the middle of its C(V) curve (whereas an unpoled ceramic has maximum C around 0V, a poled one has it off-center, thus giving useful bypass value, and radically higher energy storage, under bias), thus making a few uF look like 10s or even 100s of uF from the outside. Huge bother (complexity, cost) for not much improvement otherwise, but if you absolutely must pack something into a small envelope, or save weight -- that's one way to do it.
Especially with responsive designs like low-Q resonant and QR/BCM flyback, the amount of circuitry needed on the secondary side can be impressively low; it really shows off one possible end-goal of power supply design: to have one central energy-storage reservoir, and to transform that into usable power at the far end, as quickly and efficiently as possible. That is, if all the output energy per cycle is delivered within that cycle more or less, we only need as much output energy storage as required to smooth over between cycles -- and maybe a little extra for EMI filtering. Output stage can simply be transformer, rectifier (SR preferably for efficiency), filter, and output terminals.
Likewise for the ever-increasing speed of PoL (point of load) (DC-DC) converters: filtering requirements are less and less, and thus the cutoff frequency of the converter rises; that is, any change in load consumption, is very quickly communicated to the input side as change in current draw.
The most general takeaway is: a switching converter is a low-pass filter, an energy storage element. The less energy stored, the faster and more responsive it must be.
If you compare the voltage-mode CCM forward converters of past generations (ye olde AT(X) PSU) to now, quite a lot of space is taken up on the secondary side -- huge filter chokes, electrolytic capacitors, and probably an LC clean-up stage after that besides. Maybe 40% of total board area, when it might be more like 20% now (at least in the power section; control circuits can still take up some board area). The cutoff frequency of a voltage-mode controller is typically some kHz (for Fsw in the maybe 40kHz range; these were mostly BJT based half-bridge inverters), so the secondary-side energy capacity is huge. Nowadays with a resonant design, cutoff can be over 100kHz and mostly ceramic caps suffices for output filtering; in at least a few cases I've seen, the requirement for secondary-side electrolytics actually comes from the feedback opto's limited response speed (~10kHz cutoff?); seems insane for such an advanced design to be limited by such a silly part, but it's surprisingly hard (or slow?) to innovate in regard to opto performance.
Or kind of the converse, you could run a PFC stage on the primary and nothing else, and get essentially rectified (moderately regulated) DC at the output. That is, the power flowing through the isolation transformer is a function of instantaneous input voltage, varying during the cycle. The downside is the bulk cap's low voltage rating: higher voltage electrolytics have better energy density, so it's better to put it on the primary side instead.
Tim
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