The Altera FPGAs have a speed grade for the theoretical maximum.
The DE0 Nano's Cyclone IV is rated at a speed grade of 6, the maximum I tried to push it at was 333MHz I think the theoretical maximum is 400MHz to meet setup/hold times, but never tried to push it that much.
Yes, the PLL allows you to set any multiplier divider combination to get to your needed target clock, or close to it.
For example if I wanted a 193.16 MHz clock to drive a monitor at 1920x1200@60Hz, I will have to multipy by 4829 and divide by 1250, not sure if the PLL will let me use numbers that high (I'll try later).
Reason I selected 162.0 MHz was because of the Vesa standard at that resolution @ 60 Hz.
http://tinyvga.com/vga-timing/1600x1200@60HzI mentioned the maximum frequency because of the BeMicro documentation on accessing the DDR3 memory, it mentions the speed will be determined by the speed grade and gives the following table:
Temperature and Maximum Frequency
Speed Grade of Controller (MHz)
C6 400
C7 333
C8 333
I7 400
The OP's code is video output as well so he should be fine if he only needs 27 MHz. Set the PLL to multiply by 27 and divide by 50.
But yeah timing analysis is a pain. Thank God Quartus has good tools.