ECL Clock Divider

[linotype]

I'm trying to reverse engineer a 36 year old Trimble GPS receiver, and I've stumbled across something a bit confusing in the clock synthesizer.

The system uses a VCO generated 768F0 (F0=1.023MHz) clock as the basis for all of the other clock signals. The 768F0 clock is PLL locked (through a chain of dividers) to a tuneable 16F0 quartz crystal clock, which is PLL locked (through more dividers) to a 10MHz OCXO.

The PLLs are based on Motorola MC12040 phase-frequency detectors.

Right now, I'm trying to understand the circuitry behind the 768F0/16F0 comparison circuitry The divider chain uses two RCA CA3199 ECL ÷4 dividers to bring the 768F0 down to 48F0, which is then fed into a Hitachi HD10131 ECL flip-flop pair to... and this is where I get confused. I would think that the logical thing to do here would be to divide the 48F0 clock by three, so that the the MC12040 would be comparing two 16F0 signals.

Tracing out the connections for the HD10131 produces the attached circuit. It seems to me (and a naive simulation run confirms this) that U9B divides the clock by two, then U9A effectively just inverts the clock, which seems like a waste of a flip flop. It seems to be a ÷2 circuit, not a ÷3 as expected.

Caveat #1: This circuit uses ECL logic, and I did my simulation in a TTL simulator. ECL is quite foreign to me, and I don't know what the influence of the "pull-down" resistors is in the circuit. I know ECL can do wired-OR, but I can't wrap my head around how that might make this circuit into a ÷3 circuit. And yes, those are the values of the resistors, it seems Trimble had no qualms with using 1% resistors basically everywhere.

Caveat #2: There might be connections between pins hidden under the HD10131. I didn't check for those with a multimeter, but I probably should, but that means taking the thing apart again.

Am I missing something?

[edit] For the curious, PCB images can be found here:

http://beefchicken.com/gps/trimble/4000/sxdeepdive/10850-component.jpeg
http://beefchicken.com/gps/trimble/4000/sxdeepdive/10850-copper.jpeg

[edavid]

I think the U9A not-Q is wire-ORed to the U9B D input, making a divide by 3.

[Benta]

It's a divide-by-3, but you're missing a connection.
Connect the two "not"-Q outputs together, and the D input at U9B is then a virtual OR.
Then make the truth table, you'll see it yourself.

[linotype]

Ah, that makes sense. I should have taken a moment to do the truth table, but I was hung up in ECL being magical. Thanks for your help everyone.