I'll stop being a lurker here and solicit some feedback on a potential low cost sampler design.
Suppose we made a PCB with a signal transmission line and a sample gate line, such that the length of the sample gate line was physically longer, so the velocity down the sample gate transmission line generates the inter-sample delays. Suppose we then place multiple sampling bridges along the signal line, with the sampling gate pulse coming from the longer path gate line. It looks like using a track-and-hold design would allow the signal to feed down the signal line continuously, with the sample bridges tracking, and when we interrupted the sample gate line with a sharp trailing edge, we could close successive sample bridges at periodic intervals. This would essentially take a burst of real-time samples. We then have some slow cheap ADCs, like SPI interfaced to a micro-controller, to read the row of sample values. If you had 64 sample bridges and ADC inputs (multiplexed?), and you arranged the physical properties to give 50 ps per sample delay, that would give just over 3 ns of samples, which for 1 Ghz+ signals would perhaps be sufficient data to average together.
Some unusual things about this design would be:
1) There is no trigger, as we will collect a group of consecutive real-time samples, and use software to align them. Each batch of samples would be randomly placed from the waveform start, but you could in software extrapolate the zero crossings, which seems like is enough to align multiple samples batches. You might also use software to calibrate each sample gates signal strength, as sample gates further down the path seem like some of the signal is diverted to earlier samples. No trigger means, no high speed variable delay or time measurement needed.
2) There would only be a single sampling frequency, so this does not work at less than really high frequencies. A 300 Mhz scope is available for a non-insane price ($2600 - Rigol MSO2302A). The minimum frequency would be determined by the burst sample time, which is determined by the sample time interval (physical distance) and the number of sample bridges.
3) A quad diode bridge that looks potentially appropriate for a sampling gate (Broadcom/Avago HSMS-282P-TR1G) seems to cost about $1.50, and you would need a sample capacitor and an ADC channel. If you had 64 sample points, and could get the per sample site down to $5 in parts, that's $300 for a 64 sample collection mechanism. You would need a microcontroller to read the ADCs and output either USB data or synthesize a much slower analog signal that you feed to your low bandwidth scope (like 1ns = 1 millisecond)
4) The PCB to do all this sounds really complex, although I know boards that have 96 lanes of PCIe-3 8 Ghz signals. To delay the 64th sample gate by a few ns would take a few feet more of signal path than the measured signal path. The really simplistic board looks like a straight line for the measured signal path, and an arrays of longer and longer zigzag gate paths. This also potentially is a transmission line with 64 long stub tees, which sounds like a reflection nightmare. I suppose another question is could you have a measured signal path with 64 sample bridge taps that didn't mangle the signal.
5) Putting digital signals near analog signals you are trying to measure sounds bad, but perhaps you could stop all the digital activity before you initiated a sample burst
Even if this design seems impractical (or insane), hopefully you found it an interesting workout for your brain. It initially seemed like eliminating variable delay lines or ps resolution time measurements was a good direction, but after explaining this design I wonder if I just traded some expensive parts for a really expensive impossible to design PCB.
I don't do RF design for a living (I do high speed software). I did grow up with a parent who was an RF designer in the 60s/70s (our family business made coaxial connectors), and while other kids were learning about baseball, I was learning about TDR on a Tek sampling oscilloscope. I've recently reactivated my electronics hobby, and pleased at how easy is was to make a 2ns edge pulse generator with modern parts. Making a better one, like the avalanche transistor on a transmission line kind, would require a lot better bandwidth scope to try it out. Some people go skiing, or play soccer for fun, I guess some of us find measuring the behavior of electricity fun. I regularly write software that executes 12 billions instructions/sec (per core) so guess it seems reasonable that I should be able to easily measure 1/12 billionth of a second.
Jan