Discrete Operational Transconductance Amplifier

[InterestedTom]

So, I want a single pole voltage controlled filter, but I have decided that 0.5% distortion is pretty rubbish and I want to use a Full Scale input voltage of +-10V. I don't expect to be able to afford to get a batch of prototype ICs made. So I thought I would play around with a design I found in Johan Huijsing's "Operational Amplifiers: Theory and Design" for a class A Operational Transconductance Amplifier, adapting it for use with discrete transistors. So far I have just added Emitter degeneration resistors, to what otherwise is a differential pair with 4 current mirrors and a bias current input. For anyone who has a copy of the book, I don't plan on using 2 transistors in parallel for Q₅, so the input bias current will be equal the total current in the differential pair.

Nexperia do some reasonably priced matched transistors, some of which come connected up as a current mirror already in the package.

I was going to simulate the circuit and vary some of the matching ratios between some of the transistors, to see how matched the transistors need to be and how this affects the performance of the circuit.

What I am struggling with is choosing particular transistors to use in the simulation, obviously the end design is limited by the matched pairs that are actually available, so that is a good starting point. After that, the main variation between devices is just the typical Beta or h_FE range, how should I select transistors based on Beta aka h_FE?


Since the final application is a low pass filter I suppose another constraint would be the range of cutoff frequencies and selection of a particular load resistance and capacitance.
Anything I have missed?

[PChi]

How about using a Multiplier like the Analog Devices AD633 or MPY634? Though they are expensive.

[InterestedTom]

Because I'm a nice guy I'll share the circuit diagram:
https://photos.app.goo.gl/Z4TfaoYUmyuM5wmy1

How about using a Multiplier like the Analog Devices AD633 or MPY634? Though they are expensive.

OK: so p10 of the datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/AD633.pdf
That would work, and may end up being what I use, but I would still like to try the Discrete OTA approach to see how well that would work, and get an idea of a cost comparison.

[InterestedTom]

I'll simulate it tomorrow. I'm just wondering whether I should add some output resistance, I suppose including it in the netlist would be sensible, I can always set it to zero anyway.

[PChi]

I was under the impression that the transconductance shouldn't vary much between different transistor types. Possibly the Early Effect does though it isn't well shown in the transistor data sheets and I don't know how much I trust the models.

[LaserSteve]

Why not an OTA from That Corp instead of an expensive AD633?


Steve

[Wimberleytech]

Are you in search of a good BJT model for simulation??

[Marco]

A multiplier can be trivially wired up as a VCF, the OTA not so much.

[InterestedTom]

I was under the impression that the transconductance shouldn't vary much between different transistor types. Possibly the Early Effect does though it isn't well shown in the transistor data sheets and I don't know how much I trust the models.

The transconductance is entirely dependent on the bias current and the thermal voltage according to the book, so yes, it shouldn't vary between devices.

What is dependent on Beta is the open-circuit DC voltage gain, which will affect the Bandwidth of the closed loop response.

Why not an OTA from That Corp instead of an expensive AD633?


Steve

I will try and remember THAT in future. I will still have a go at netlisting the circuit diagram and fiddling with transistor parameters, even if it's just as a learning exercise.

[InterestedTom]

A multiplier can be trivially wired up as a VCF, the OTA not so much.

A capacitor to ground at the output, followed by a voltage buffer. Gain control using Negative feedback from the output of the voltage buffer to the inverting input of the OTA. Voltage buffer could be a simple BJT emitter follower for reduced cost, may have to be a current source biased emitter follower at the cost of another transistor if distortion is too high at high frequencies and/or high gains. Open loop gain will still be Bias current dependent, as would closed loop bandwidth.

[InterestedTom]

Are you in search of a good BJT model for simulation??

Sort of, I would really just like a passable free one so I can get an idea of what value emitter degeneration resistors are required to cancel out the typical manufacturing errors in between transistors in my circuit.

[T3sl4co1l]

So far I have just added Emitter degeneration resistors

Oh, well it's not an OTA anymore...

You get OTA functionality from the nonlinear r_e.  When R_E is fixed by swamping with an external resistor, gain saturates and output is no longer proportional to the control current.

(If you meant for the mirrors, not diff, that's fine!)

Distortion can be reduced arbitrarily by reducing the input signal level, but eventually noise will dominate.  OTAs are not renowned for SFDNR.  You may be better off with an MDAC architecture or something like that.  (If you don't want steps, the steps can be interpolated with an OTA or JFET; distortion of the active device is reduced by way of its being a smaller part of the final signal.)

Nexperia do some reasonably priced matched transistors, some of which come connected up as a current mirror already in the package.

Note they are separate die parts, and the datasheet specifies typical mismatch under load conditions.

This can be alleviated (by about a factor of hFE) with a cascode structure, e.g. Wilson current mirror.

You have one advantage over the classics (e.g., LM13700), good PNPs.  Otherwise, the matching and temp tracking is pants.

I was going to simulate the circuit and vary some of the matching ratios between some of the transistors, to see how matched the transistors need to be and how this affects the performance of the circuit.

Don't forget to adjust TEMP as well as W.  (Ideally TEMP would be a function of device power and thermal time constants, but that's nontrivial to do.)

What I am struggling with is choosing particular transistors to use in the simulation, obviously the end design is limited by the matched pairs that are actually available, so that is a good starting point. After that, the main variation between devices is just the typical Beta or h_FE range, how should I select transistors based on Beta aka h_FE?

It really doesn't matter.  You're after the basic (Ebers-Moll or Gummel-Poon model) behavior.  You can use the default SPICE model if you like.  Any general purpose transistor, near what you're going to use, will do.  Power transistors will have too much capacitance, and may have too little hFE at low currents (if recombination is even modeled).  Other than that, you have a good 6-ish orders of magnitude to work within.

Tim

[InterestedTom]

So far I have just added Emitter degeneration resistors

Oh, well it's not an OTA anymore...

You get OTA functionality from the nonlinear r_e.  When R_E is fixed by swamping with an external resistor, gain saturates and output is no longer proportional to the control current.

(If you meant for the mirrors, not diff, that's fine!)

But the output current is still controlled by the bias current and the input voltage, so it's no longer an OTA, but it does form a low pass filter with an output capacitor and the bias current controls the output current, which controls the gain frequency response. NFB will control the closed loop gain, but the open loop gain won't vary with I_B. It still has transconductance: I_out/V_in. But the transconductance isn't controlled by I_B.

I don't see why you would be mistaken so my circuit is a transconductance stage, with current mirror output, which has a variable bandwidth when supplying a capacitive load. But the variable transconductance gain (in this case unwanted) is no longer present.

That's not bad for a late afternoon sketch on a piece of paper...

[InterestedTom]

That's not bad for a late afternoon sketch on a piece of paper...

This sounds arrogant, sorry if you took offence.

[T3sl4co1l]

A diff pair with emitter degeneration, R_E >> r_e, has fixed gain, ~independent of bias.  More bias only reduces r_e, but R_E remains fixed, hence small-signal gain remains ~fixed.

What you're varying, is simply maximum output current.  In a conventional dominant pole opamp, this sets slew rate.  But this is only relevant at clipping, so you must avoid that to meet your distortion spec!

NFB isn't applicable either, because that acts to stabilize overall gain, under variation of amplifier gain.  Unless there's an active feedback configuration that's not coming to mind (quite possible!).

That's why most ICs provide linearization diodes -- the undegenerated diff pair has a tanh(x) transfer function; the log(x) behavior of the diodes serves to flatten this out somewhat, of course the tanh must dominate for larger arguments so it's only a modest improvement (30-60mV versus ~10mV at the input terminals).

You can also do a switched capacitor filter, which might be more linear than an OTA can provide, with the downside of a hard upper frequency cutoff set by the clock rate and sampling behavior.  Consequence: if you want that 1-pole response (-20dB/dec) to be clean and smooth at frequencies very much higher than f_c, the clock frequency needs to be placed accordingly, which makes the circuit a bit more ungainly (charge injection --> DC offset?).  Although, for a single pole, I don't think that's much of a problem?  So that might be an option.

Tim

[InterestedTom]

OK, thanks for pointing out my mistake, I could have been chasing my tail for a bit there.

Does it matter whether the substrate node is connected to ground (which is default in ngspice) or connected to it's own net, i.e. left floating? What would the manufacturer connect the substrate node to inside the device package?

[InterestedTom]

You can also do a switched capacitor filter, which might be more linear than an OTA can provide, with the downside of a hard upper frequency cutoff set by the clock rate and sampling behavior.  Consequence: if you want that 1-pole response (-20dB/dec) to be clean and smooth at frequencies very much higher than f_c, the clock frequency needs to be placed accordingly, which makes the circuit a bit more ungainly (charge injection --> DC offset?).  Although, for a single pole, I don't think that's much of a problem?  So that might be an option.

I wouldn't have thought of this, I didn't realise how good they can be. I'm now looking at the LTC1043, this is probably what I will use.

[T3sl4co1l]

Discrete transistors have substrate open, or tied to collector.  Monolithic arrays have substrate on a pin (usually?), which should be the lowest voltage in the circuit (usually GND).

AFAIK, substrate is only modeled as a diode, so can be ignored (open circuit) for most purposes.

Tim