HI
trace length account on all chip lay of physic not only apply to FPGA ,but now it tend to dispersal form datasheet since it use BGA ram chip that less susceptible
that old package ,but fact remain signal must travel this distance to
and yes usually on high end CAD package you not put the length of the trace ,but the formula ,then it become bit dynamic ,but on my side still work old way whit external calculator
dielectric consten was for calculate trace spacing / impedence calculation
trace lenght ,was for timing skew ,so only need raising/fallinh time speed and material propagation delay (% of speed of light)
Ex: when you latch data into bus you what that all signal was set on the ram chip input , may seem strange at first but if bit D3 have 10mm to long ,signal was late versus the other
so it will not latch whit good value
,
same for clock it ussualy 2 clock whit 90 phase shift and it use falling and raising edge so it actually 4 state change per true CLK MHZ ideally each spaced by 25% of the desired clock
but it one trace was bit longer all quadrature timing become screw
__|--|__|--|__|--|__|--|__ < Clock A = 666mhz
_|--|__|--|__|--|__|--|__ < Clock B = 666mhz 90 out of phase
combined it make 1333 whit 50% duty cylcle but as soon A or B move duty cycle go away really fast ...
so you have 2 chalenge
1-) have really good impedance match every were for avoid signal bonce and reflection that make ghost signal on he bus
2-) have the right timing for clock generation and bit timing
not forgot that Dram was dynamic so it refresh in permanence if bus was not perfect it start soon to be error and quickly fail to work so it have but that work and bus that fail
and at clock of 1333Mhz that look instantaneous