You said "power supply ESL" and I didn't quite get that you meant the power leads in the package.
Yes, sorry, everything counts. As far as I understand, it's simply a resonance of the LC circuit formed by the internal capacitance of all the MOSFETs in the IC and any inductance present along the way between the power supply terminals on the IC (package pins + PCB + external capacitors). This resonance causes the power supply voltage seen inside the chip to vary and hence the output varies too. BTW, the newer logic families likely have less internal capacitance which could be another reason why the 74LVC1Gxx gates ring less.
I just used the minimum to ensure that absolute maximum ratings are not exceeded.
I'm kinda burned out but what do you mean by this?
Look up "absolute maximum ratings" in the datasheet
![Wink ;)](https://www.eevblog.com/forum/Smileys/default/xwink.gif.pagespeed.ic.cldandycH0.png)
There is also "recommended operating conditions"; I think I actually designed to stay within the recommended limits under normal operation and below absolute maximum under output short circuit to ground.
I'm planning on using 0201 resistors (Vishay has a whitepaper where they show better frequency response with smaller package size) as well.
Be careful with power dissipation. I used only two channels and two resistors and made them with doubled 0805 to be on the safe side.
By the way, I think you should add vias near GND pins of the driver chips (assuming the bottom is ground). Otherwise the return current has to take a round trip around the whole bunch.