Half Bridge Layout

[PsychedelicBreakfast]

I've been tasked to find the real world performance of a few Half-Bridge drivers. The drivers share the same pinout so I've decided to lay out a proper PCB for one and then test each empirically. Because of my inexperience I am finding it a bit difficult to see if I have an optimum layout. From the research that I've done it seems that it's paramount to reduce the loop area of the high-side's bootstrap cap and also between gate signal (to the high side) and it's return path (HS). Here's how I've done it:

Note that this is a 2-layer board the bottom is a GND polygon but I have not shown here to make it easier to see other signals. C9 is the bootstrap capacitor. NetR9_1 is the return path of the driver's high side output. Notice that it is beneath the FET's gate path to reduce the loop area. Since the low-side's return is just connected to GND I let the GND plane handle the return signal. This should automatically ensure that the return signal follows the path of least impedance (I hope...).

The frequency of operation that I'm aiming for is 20 KHz with rise times in the vicinity of tens of nanoseconds (hence my focus on the layout). I am still unsure of the value of the bootstrap capacitor I should use. Perhaps 100nF? Would appreciate some advice on this.

So since I need to give this layout for fabrication I just wanted to ask here if I'm missing anything or if there's anything I can do to improve this layout still. The Half-Bridge driver in consideration is the MIC4102 and MAX51018.

The drain pads of the SMD FETs are so large because of the smt heatsink.