Analog switch datasheet parameters

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Hi folks,

I'm working on a project (description is irrelevant), but it has multiple feedback paths and they are routed using analog switches. There are a few parameters that I don't understand, off- and on-leakage current and off- and on- capacitance. I understand their origin, for instance, leakage arises from the leaky protection diodes and capacitance arising from FET parasitics. The trouble I'm having with these parameters is understanding the different between the on and off parameters.

This is one of the switches I'm using: http://datasheets.maximintegrated.com/en/ds/MAX4541-MAX4544.pdf

It has two parameters COM_ Off-Leakage Current and COM_ On-Leakage Current. What is the difference between these two?
Same goes for capacitance.

Furthermore, what is NC_ NO_ Coff capacitance? Is this when that channel is off, the input signal still sees some capacitance?
Thanks a bunch!

[T3sl4co1l]

There's leakage and capacitance between the terminals of the switch(es), and between each terminal and the supply pins.  These should be (in effect) what they are describing.

Tim

[tree]

I understand the origin, I just don't understand how these parameters relate to those. For instance, what in the world does COM_ Off-Capacitance describe? This surely can't be the small signal cap to ground at that pin because COM is never "off". Could this possibly be Cds of the switch that's off?

Here's another thing I don't understand. For a switch that's on (MAX4544), is the small signal cap (to ground) before or after rds?

I've seen some datasheets that list the on capacitance at the drain AND the source, so do I just use one (depending on signal directionality) or do I need to include both of those of those in my frequency domain analysis?

Take this datasheet for example, http://www.analog.com/media/en/technical-documentation/data-sheets/ADG884.pdf

This one has much easier to understand parameters, Cs(off) and Cd,Cs(on). Okay, now we're cooking with fire, BUT do I include Cd & Cs of ~300pF at each pin or just one in my signal path?

The reason why I need to know how to model these for frequency purposes is that I have a constraint on my bandwidth, which is 100kHz and my signal chain has quite a few poles and zeroes, so I have to make sure that my response is nearly flat up to my BW and then I don't really care what it does as long is it maintains a minimum 20dB/dec attenuation.

[T3sl4co1l]

I understand the origin, I just don't understand how these parameters relate to those. For instance, what in the world does COM_ Off-Capacitance describe? This surely can't be the small signal cap to ground at that pin because COM is never "off". Could this possibly be Cds of the switch that's off?

It could be COM alone -- they might be able to measure parameters on the die that aren't available once it's pinned out in a package.

However it is they're measuring it, it seems like that's what they're talking about, just the total, versus each at a time.

Fig7 ignores SPDT action, but implies that the other pins are "do not care" during a given test, so the capacitance of a pin includes the capacitance from pin to pin and both pins to ground.

There's also an effect where the capacitance of the channel itself varies (when off, electrons are in fact prohibited from occupying the channel, so its capacitance to substrate is low, whereas, when the channel is "on", it does have capacitance against the substrate, like a regular PN junction), so you should expect C_on > 2 * C_pin.  Which seems to be the case.

Here's another thing I don't understand. For a switch that's on (MAX4544), is the small signal cap (to ground) before or after rds?

Yes.  Both.  A CRC pi filter should give a reasonable model of the frequency response.  A more nuanced model might be: C1-R1-C2-R2-C3 (pi topology, extended), plus C4 spanning between input (C1) and output (C3).  C1 and C3 are pin capacitances to ground, C2 is channel capacitance to ground, C4 is pin-to-pin capacitance (in the off state).  R1 + R2 = Rds(on), which varies with state.  In principle, C2 also varies with state (as mentioned), but for most purposes, it should be accurate enough to vary R1 and R2, since that effectively connects C2 to the rest (or not).

Note that it's not especially good (page 5, bottom left).  It's already 1% (i.e., -40dB) at 15MHz, and the insertion loss is something like 1.5-4dB (because on resistance is comparable to system resistance -- note the test was done at 50 ohms!).  The "off loss" curve will shift up proportionally for higher system resistances: for instance, if you did this for 1kohm audio applications, you'd expect it to cross -40dB at about 2MHz.

The reason why I need to know how to model these for frequency purposes is that I have a constraint on my bandwidth, which is 100kHz and my signal chain has quite a few poles and zeroes, so I have to make sure that my response is nearly flat up to my BW and then I don't really care what it does as long is it maintains a minimum 20dB/dec attenuation.

That should be fine, but alas, frequencies are useless without impedances also!  So you'll have to compare those against the switch's impedances.

Tim

[edavid]

I understand the origin, I just don't understand how these parameters relate to those. For instance, what in the world does COM_ Off-Capacitance describe? This surely can't be the small signal cap to ground at that pin because COM is never "off".

It looks like cap to ground with the other switch pins open.  Ask a Maxim apps engineer to be sure.

Could this possibly be Cds of the switch that's off?

These are CMOS switches, with at least one drain and one source connected to each pin, so it doesn't make sense to talk about Cds.

[tree]

I thought about it some more and realized what COM_ Off-Capacitance is. Some variants just have SPST and so COM_ can be off. DUH!

So I found a switch from Maxim that has the same type of parameters and has a model available. So I started to play with the macromodels as well as putting together my own model together. What I found is that On Capacitance typically is the sum of Csb, Csg, Cdb, Cdg, for both PMOS and NMOS of the transmission gate. Since rdson is relatively small, we can ignore the HF zero and just lump those capacitances into one, which is what it seems the datasheets do anyway. To get an accurate model, as you said, Tim, a CRC pi filter is adequate, where each C is approximately 1/2 of the datasheet's Con. This provides a reasonably accurate model that's good to well more than 3 orders of magnitude above my BW at which point other impedances come into play, but even then, the deviation is a few dB, and by now we're well into the GHz range.

I'm not worried about resistive loss since I'm driving a high impedance amplifier on the other side.
Off loss is of no concern because I have other filters in my system that kill anything >100kHz

I'll leave this app note here that describes analog switches in more detail for those interested: https://www.intersil.com/content/dam/Intersil/documents/an55/an557.pdf

edavid,
Cds exists through substrate coupling, but it's extremely small so usually neglected.