(Yet Another) DIY Multislope ADC

[Ecogeek]

I've been researching the ADC in the HP Agilent 34401A  the MUX switch HC4053 seems to be operated in the most non-linear slope of the Ron/V curve. I know operating into a virtual ground, gives the voltage around +/- 20mV, but the Ron slope still is very large and will impact on the voltage to be measured. The manufacturers vary in specifications quite a bit so device selection is important. You are correct the non-SOIC -16 packages that are now available TMUX4053 and your choice are significantly improved in Ron and linearity.   I also do not understand why HP in the 34401A ground the VEE instead of connecting it to -5Volts giving the Ron Voltage close to the middle of VCC-VEE with the lowest Ron and lowest resistance slope?
This is not to mention the high variation change in R between channels at the lower VCC-VEE voltage, and not to mention the resultant TC  with varying channel Ron. 

Others with more knowledge may wish to add why the 4053 device seems to work so well in several legacy HP equipment when the device data shows it could be much better operating at a greater VCC-VEE range, and if it was possible to use some of the newer MUX would/should be exceptional?

[Kleinstein]

The voltage at the switch is still relatively small and with a 5 V supply for the HC4053 the nonlinear part is not that bad. It still give a little U² contribution to the ADC result. The 34401 uses a rather low input current with 100 K at the input. I have tested the HC4053 in comparison. With 50 K input resistors the square part is barely visible. With more current (e.g. 20 K for a 10 V range) it gets significant.
The main point helping is getting a lower R_on - here the LV4053 has about 1/3 the R_on and thus corresponding less (scales like  (R_on/R_input)² ) nonlinear part.

Speed wise the 74HC4053 and even more the LV4053 are quite good, compared to DG419 or similar, more analog oriented chips. This may well help with jitter.
The lower voltage FET switches have usually a better ration of Ron to capacitance and often also higher speed.

The TMUX1133 has very low R_on, but slightly higher capacitance. So these chips would want a smaller input resistor. One than has to watch out more for resistor self heating as a nonlinear effect.
So they may be an option if a lower resistance is wanted (e.g. a smaller voltage range, like 5 V or for super low noise).

I don't know why HP used no -5 V. A point here could be the charge injection: this is quite good near the negative supply. It could also be as simple as not having a -5 V supply and it may not be worth it. After all the MS3 in the 34401 is more designed for low cost, not for high performance.
The resistance is usually quite high in the center of the range and the chage injection also changes with voltage.

Testing jitter for the CMOS switches could be similar to logic gates, switch between 2 voltages. This would slightly different from just current steering, but close.

I have seen slight variations in the ADC noise with different brands / types of 4053 switches (Cd4053, HC4053 (TI + ST),  max4053 and LV4053). The LV4053 was on top with noise and Ron/linearity and the leakage was also good. It may not be the absolute best switch chip, but pretty good and cheap / easily available (even as DIP).

[NNNI]

I'm not quite sure if I understand exactly what causes the U² INL error. I was initially advised that it could be because of power coefficient of the reference resistors (and hence the quadratic shape). Is it the temperature coefficient of the analog switch that is much larger than that of a resistor network like the NOMC (which specifies +/-25ppm max. absolute tempco [1]) and therefore contributes more to the INL for a given current and power dissipation, or is another mechanism at play?

I did some back-of-the-envelope calculations for the switch/resistor configuration I used in my latest design (10K NOMCT/TI SN74LV4053): (100/10K)² which is 100ppm, and that's approximately what I got as the peak of the ADC's INL quadratic curve.

[1]: https://www.vishay.com/docs/60007/nomc.pdf

[Kleinstein]

A U² term comes from the nonlinear on-resistance of the CMOS switch for the input signal. As an approximation the voltage drop on the on resistance partially subtracts from the effective gate voltage. This makes R_on to go up with a positive input current and R_on go down with a negative input voltage.  The voltage drop is small and thus a mainly linear effect on the resistance and thus linear effect on the gain (or actually 1/gain). A linear change in the gain gives a U² contribution. To get rough numbers one could look at how R_on changes with the supply voltage or the signal voltage.
With 10 K of resistance with a LV4053 one would get quite some INL - at least with a 10 V full scale range and likely already at 5 V.

The termal effect gives a U³ part. Here the change in the resistance is proportional to the power and this U². The added term to the result is thus 3rd power. As a thermal effect it is a delayed effect. It takes a few seconds for the resistor array to warm up.  The relevant TC should not be the absolute TC, but the TC matching: the same change to the input and ref. resistors would cancel out. From my experiance the TC matching is often quite good (e.g. 1 ppm/K range) for the resistor arrays with an intermediate resistance (5 K to 100 K). The DS values seem to be for the whole range of resistors, with more effect of the bond wires for the lower value resistors.

The switch on resistance has a high TC, but there is usually also matching between the input and the ref. channels. Also the switches are only a small part of the total resistance.

[NNNI]

As for the switch capacitance, I assume it would mostly affect the reference switching. The switching times are then limited to how quickly the switch common terminal charges up to Ron*Iref.

[Kleinstein]

The capacitance at the input switch should not be that relevant, as it is not operated that often. Usually the swiches for the input and references are the same anyway to get compensation of R_on drift.
The swiching times are usually longer than just Ron*C_switch. Chances are a large part is from the gate drive stage with a significant higher resistance. So it is more that internal stage to set the speed.
R_on * C_switch woud be some 20 ohms * 10 pF = 200 ps, which is faster than the actual swiching speed.

The speed on fast the ref. input node settles to the new voltage is also determined by the integrator - usually the integrator input is not a perfect virtual ground, but needs some time (e.g. 100-500 ns) for the integrator input to settle. The swich common node is also normally aready at R_on*Iref, as the same I_ref is flowing essentially all the time, just switching between the 2 paths. It is more typical to have a short break before make time in which the node can charge up even higher. The capacitance here limits how far the voltage spikes.  A few ns time a fraction of 1 mA would be on the order of 1 pC of charge pulse, somewhat comparable to the swiches own charge injection.

[NNNI]

I think it's finally time for an update.

I've spent the last three weeks working on this project again, and I'm happy to report that I have solved all software issues so far. It's amazing how after a year of working with the RP2040, I was able to come back to this project and get it up and running in no time! I also have to thank iMo for the suggestion of using set pins for both reference switches and the input switch, it saved a few instructions. While I was at it, I also optimized the runup code to use fewer instructions.

First, I was able to move the residue ADC reading code to PIO, and I have synchronized it with the runup PIO code via interrupts. I replaced the MCP3202 with the MCP3201, since the second channel was unused, and the two-channel version needed configuration. Switching to the single channel version simplifies the code.

The second big change was to reduce the modulation frequency from 300kHz to 75kHz. I took a closer look at the scope waveforms, and the integrator summing junction didn't settle to a reasonable level in the short constant phase of each runup cycle. I also tweaked the voltage divider between the two OPA140s while looking at the output of the first stage op-amp to obtain an optimum response. That happened with a divider of approximately 4kΩ/1kΩ. I have attached a scope screenshot that shows the first stage op-amp output on Ch2 (cyan) with 10kΩ/1kΩ, you can see how the rising edge is rather slow and has an RC-like curve. After tuning the divider, the spike is still present but the curve goes away. I wonder if I could implement more advanced compensation, but I am not sure how I would do that.

With just runup and residue, the resolution is rather limited, with around 50μVpp noise in the readings, plot attached.

I also implemented Kleinstein's idea for fast rundown (I learned that this originated in the 3456A meter) to reduce the range of voltages that the residue ADC has to digitize. One advantage here is that the scaling buffer amplifier in front of the ADC has to amplify the integrator voltage instead of attenuate it, which should reduce the residue ADC's referred-to-input noise. A waveform with 5 runup cycles is attached, you can also see the fast rundown at the end after a short dwell time. Ch1: integrator, Ch2: input switch control, Ch3: -ref switch, Ch4: +ref switch.

With that change, the noise has gone down quite a bit. The second plot attached has units of LSBs, I will change the code in a bit so the readings are in volts. But based on some rough calculations, looks like the noise is around 2μVrms or around 13μVpp.

Here are the formulas used to calculate the counts:

Code: [Select]

Step 1:
N1 = n_neg*(7*RUU + 1*RUD) - n_pos*(1*RUU + 7*RUD)
where:
n_neg - number of times the negative reference was turned on
n_pos - number of times the positive reference was turned on
RUU   - residue counts corresponding to 1/8 runup 'up'
RUD   - residue counts corresponding to 1/8 runup 'down'
(fast rundown has a 1/8 runup cycle resolution)

Step 2:
N2 = n_rundown_neg*RUU - n_rundown_pos*RUD
where:
n_rundown_neg - number of 1/8 runup units the negative reference was turned on
n_rundown_pos - number of 1/8 runup units the positive reference was turned on

Step 3:
N3 = residue_before - residue_after
where:
residue_before - residue ADC reading before runup
residue_after  - residue ADC reading after runup

Step 4:
FINAL = N1 + N2 + N3
where:
FINAL - final result, in units of residue ADC counts
N1    - runup counts (in terms of residue ADC counts)
N2    - fast rundown counts (in terms of residue ADC counts)
N3    - residue difference (in terms of residue ADC counts)

Final result is in terms of residue ADC counts, equivalent to an LSB

The residue ADC is calibrated by switching +ref and -ref to the integrator for 1/8 runup period and measuring the difference in integrator voltage before and after. This is because the fast rundown resolution is 1/8 of a runup cycle (runup has a 1/8 or 7/8 duty cycle).

There's a few more modifications and improvements I'd like to make to the circuit, I will post an update regarding that later.

The latest C code for the RP2040 can be found in the project repository: https://github.com/NNNILabs/Multislope-3I/tree/main/SW
There is also a file called project.log in the SW folder. It's just a text file with a little more details on what modifications I made on what date.

[Kleinstein]

For the integrator compensation the divider between the 2 OP-amps is one part. The other part to adjust / trim is some RC series element to ground at the integrator input. This can help dampen ringing. The divider 10K/1 K may be a bit sluggish, not very fast, but should still be stable.
With 4 K / 1 K one may be on the fast side with likely quite some ringing.
For a first idea on the compensation one could at a simulation instead of real hardware. The question here is how well details of the OP-amp like output impedance are modeled.

The scope picture still has quite same fast oscillation / ringing as background. This could be from the µC / a ground loop or a probing issue.
The settling time for the integrator should be on the order of 500 ns to maybe 1 µs for the slow version.

A timing resolution of only 1/8 if the 75 kHz run-up cycle looks low. I would have expected a modulation more like 1/32 or 31/32 for the lower frequency.

[NNNI]

Because I have already pretty much reached the limits of instruction memory, 1/32 and 31/32 would be very hard. However, 1/16 and 15/16 is certainly possible. What concerns me in the latter case is integrator settling. The fixed part at the start of the runup cycle is only (1/75kHz)*(1/16) = 833ns. I would have to make a lot of optimizations to the integrator to get it to settle in that time.

The board already has a 100Ω/100pF (the values were an arbitrary choice and were not calculated/simulated when the board was designed) damping network at the summing junction. The spikes on the output of the first stage op-amps are not because of a probing issue - I had a similar suspicion, so I used the ground spring, but the spikes were still there.

I've already simulated the configuration in LTspice, although I'm not sure to what extent I could trust the simulation. I've attached the .asc file if someone wants to take a look. You might need to download the OPAx140 SPICE model from the TI website and remove the unnecessary .inc statements.

[NNNI]

I increased runup resolution to 1/16 and 15/16. That resulted in a smaller residue voltage after fast rundown, so I had to increase the gain of the scaling amplifier for the residue ADC, that gave me a boost in resolution.

I also tried another runup scheme (see attached image, 'Runup 2') suggested to me by Jaromir. The fixed parts at the start and end of each cycle should have 0 current flowing into the integrator (apart from input current, and reference mismatch during the first constant part), because the references are on or off at the same time. The middle variable section depends on the comparator state. this method only causes a 0V to ±Iref step into the integrator, instead of the -Iref to +Iref step with the complementary PWM runup ('Runup 1' in the image).

These changes resulted in a noise (with shorted inputs) of 1.87μVrms.

[Kleinstein]

The runup pattern 2 can have a slight added effect from the state of one reference effecting the way the integrator settles to the changing the other reference. For the transients it can make a small difference if the positive or negative reference is switched first. The effect may well be small enough to be not an issue. At least this adds up proportional to the signal and thus a more a gain effect to the run-up steps.
A similar effect applies to the settling effect with short pulses in the 1st run-up scheme. This number of pulses scales with the signal and thus a similar possible effect.

A setting with 1/16 and 15/16 would also effect the useful range at the input. This gives 14/16= 7/8 of the reference as usefull range. the 1/8 and 7/8 only allow for 6/8 = 3/4 of the reference range and thus may need a higher ref. or smaller resistors for the reference paths. At least it get hard to get +-10 V with a +-14 V reference.

1.9 µV of RMS noise is not bad, but also not great.

[iMo]

..
These changes resulted in a noise (with shorted inputs) of 1.87μVrms.

At which NPLC is the noise measured?
Greetings to Jaromir

[NNNI]

Apologies for not mentioning that, all measurements so far were done at 1 PLC.

[iMo]

Afaik Jaromir did 0.6uVrms with 10NPLC in his design in past.
1.9uV/3 = the same, imho..
PS: my 34401A does 0.7uVrms at 100NPLC (while measuring the ADR1001).

[NNNI]

As Kleinstein mentioned, there is still some room for improvement.

For example, I am not using flip-flops and an external crystal oscillator to 're-clock' the runup switch signals from the MCU yet, I am expecting a significant improvement after that change. The resistor network is still a 10kΩ NOMCT, so the reference currents are ±1.4mA. INL because of Ron modulation or PCR in this case will be rather large, that is yet to be tested. The integrator is also presented a significant dynamic load. Increasing the resistor network to 50kΩ should in theory reduce both problems and decrease noise (perhaps not as much) and reduce INL. The current board also uses an LM399, which I will be replacing with an ADR1399.

[iMo]

Yep, ADR1399 is 2x better than 399 noise-wise, also the switcher in your 2040 has to be eliminated. Try to power up the whole stuff off the batteries (not the external battery banks as they may contain a switcher too, but plain Nx18650 with linear Vregs)..

[NNNI]

The switching regulator was the first thing to go, that has bitten me too many times now! The 3.3V rail is being powered by an LDO now, and the entire board from a bench power supply (which is, of course, linear).

[iMo]

The switching regulator was the first thing to go, that has bitten me too many times now! The 3.3V rail is being powered by an LDO now, and the entire board from a bench power supply (which is, of course, linear).

But the linear bench PSUs leak as well
Try with batteries (and put the batteries inside your cookie box as well).
PS: Like 5+5 pieces of 18650 Li-Ion (+/-21V max) 4 lin Vregs. for +15V, -15V, with a tap at +8.4V for 5V and 3.3V I suppose..

[Kleinstein]

For the start the linear bench supply can be OK. The switcher at the RP2040 could add jitter and clock variations. Not sure how much, but an external clock could get rid of that and than the switcher may not be that bad. Still the expternal clock would want a stable supply too and not really the switcher.
It would be mainly for later use that battery supply or a low leakage transformer / SMPS would be an issue. For the initial test the more normal supply should be OK.

When doing a test with a short or the internal reference, the ref. noise is not that important. It gets an issue when reading an external voltage though.

For the noise level the 34401 should be around 2 µV_RMS for 10 PLC. So getting a slightly better noise level with 1 PLC is not that bad.
Still other modern meters like KS3446x are more closer to 1 µV.

The clock could be part of the noise source due to the PLL, that may not be super low jitter.
This is not just about jitter, but the clock at the µC could also get modulated depending on the signal and thus add INL errors. I have seen that with my AVR version gettting an INL error on the order of 20 ppm from that (an external clock fixed that). Even than small interference from the UART / µC internal ADC were detectable without an external flip flop.

With a ref. current of 1.4 mA one could get low noise, but at the cost of extra INL errors. Increasing the resistor network for the integrator input to 50 K would add some noise ( ~ 300 nV RMS noise from the resistors, not much compared to 2 µV, but still the main principle noise sources).
I consider 50 K a reasonable compromise among the available standard values.

[iMo]

An anecdotal comment - I remember issues with the atmega1284 (a nice mcu, btw) where the adjacent serial RX and one of the crystal clock pins caused malfunction of the bootloaders when the oscillator was set for a lower swing mode (lower current). Setting the xtal oscillator to the high power mode cured the issue..

..I have seen that with my AVR version gettting an INL error on the order of 20 ppm from that (an external clock fixed that). Even than small interference from the UART / µC internal ADC were detectable without an external flip flop..

[jaromir]

Afaik Jaromir did 0.6uVrms with 10NPLC in his design in past.

Attached is sample run of ~180 samples at 1PLC - that is not only ADC, but complete voltmeter with input amplifier, switching, overvoltage protection and related stuff. Standard deviation is ~700nV.
Just for a good measure I attached INL sweep of my latest voltmeter creation.

Sorry for digressing.

[iMo]

@Jaromir: Hi, thanks, so my memory was wrong!
Your 700nVrms at 1NPLC means aprox 210nVrms at 10NPLC and 65nVrms at 100NPLC, am I right?

[jaromir]

At 10NPLC it is roughly like that (~200nV measured), 100NPLC is already in the region of quickly diminishing returns, due to the increasing influence of 1/f noise.
For practical measurements I typically use autozero-ed 10PLC sampling (to get rid of the 1/f noise) and average of multiple samples instead of longer than 10PLC integration period. AFAIK this is common approach used in commercial meters.

I would suggest discussing this or other aspects of my ADC in one of the multislope threads, or at our annual technology meeting in Kingstown.

[iMo]

Ok, thanks, I've just remembered the coef is aprox 3x when going 10x with NPLC.
And sure, let us meet in the Rawacou Park pub before the Meeting..

[Kleinstein]

For the longer integration and especially with averaging it makes sense to look at the data with auto zero mode. This suppresses much of the 1/f noise, but adds factor of square root 2 to the white noise. For the data it abviously makes sense to note which case is used.

The DMM front end may also add noise - that data for the DMMs are obviously for the complete meters and not just the ADC. The simple protection with 100 K ohms series resistance and a balancing 100 K in the zero link would add (add as squares of cause) some 300 nV RMS to 1 PLC Az mode.