Your ADC shoots the data out with 120 samples per second automatically. Therefore you see a lot of pulses (RDY) there spaced around 8-9ms.
The output rate is predetermined based on the package option (MAX11201A at 120sps and MAX11201B at 13.75sps).
You have to read the datasheet:
The RDY/DOUT is used to signal data ready, as well as reading the data out when SCLK pulses are applied. RDY/DOUT is high by default. The MAX11201 pulls RDY/DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at the SCLK input. On applying the clock pulses at SCLK, the RDY/DOUT outputs the conversion data on every SCLK positive edge.
To monitor data availability, pull RDY/DOUT high after reading the 24 bits of data by supplying a 25th SCLK pulse.
You have to poll the RDY, when it goes low (data ready) you have to clock in the SCLK and you get the data out. With 25th pulse you set the RDY to high, and again, wait for the next data ready by polling the RDY (for example - in a "while{}" loop wait until RDY is low, or, use an interrupt triggered by the falling RDY edge).
Your SCLK "period" cannot be longer than 300us (reading all the data bits must fit into 1/120sps), I guess. Use HAL_Delay_Microseconds, for example 10us in your code above, to be on the safe side..
Pseudo code, for example:
set SCLK = 0;
data = 0;
while ((read RDY) == 1) {}; // wait on RDY == 0
for (i=0;i<24;i++) { // read 24bits, MSB first
data = data << 1;
set SCLK = 1; // data from DOUT on rising edge
delay 10us;
data = data + (read RDY);
set SCLK = 0;
delay 10us;
}
set SCLK = 1; // set RDY to 1 with 25th SCLK
delay 10us;
set SCLK = 0;
delay 10us;