Hey guys,
Thanks for helping me out.
This is the code i'm using for the F0 discovery:
#include <stm32f0xx.h> //stm32f030f4
#include "stm32f0xx_rcc.h" //we use rcc
#include "stm32f0xx_gpio.h"
#include "stm32f0xx_flash.h"
//connection
#define LED_PORT GPIOC
#define LED_A (1<<8)
#define LED_C (1<<9)
void SystemCoreClockHSIPLL2(uint32_t RCC_PLLMul_x) {
RCC_DeInit(); //reset rcc
RCC_PLLCmd(DISABLE); //disable PLL
RCC_HSICmd(ENABLE); //enable hsi;
RCC_HCLKConfig(RCC_SYSCLK_Div1); //set sysclk divider
//RCC_PCLK1Config(RCC_HCLK_Div1); //set pclk1/2 dividers
//RCC_PCLK2Config(RCC_HCLK_Div1);
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
FLASH_SetLatency(FLASH_Latency_1);
FLASH_PrefetchBufferCmd(ENABLE);
RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_Div2, RCC_PLLMul_x); //configure pll / divider. _x=[2..16]
RCC_PLLCmd(ENABLE); //enable pll
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) continue; //wait for pll to be ready
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //set pll as sysclk
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL/*0x08*/) continue; //wait for PLL to be ready
SystemCoreClockUpdate(); //update SystemCoreClock
}
//delays some
void delay(uint32_t dly) {
while (dly--) __asm("NOP");
}
int main(void) {
SystemCoreClockHSIPLL2(RCC_PLLMul_12); //go to 48Mhz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
GPIO_InitTypeDef gis;
gis.GPIO_Mode = GPIO_Mode_OUT;
gis.GPIO_OType = GPIO_OType_PP;
gis.GPIO_Pin = LED_A | LED_C;
gis.GPIO_PuPd = GPIO_PuPd_NOPULL;
gis.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(LED_PORT,&gis);
LED_PORT->ODR &= ~(LED_A);
LED_PORT->ODR |= (LED_C);
while(1) {
LED_PORT->ODR ^= (LED_A | LED_C);
delay(1000000);
}
}
The code for my board differs only in led pins.
When i set the multiplier at 2 and at 12, the discovery board shows remarkable difference in toggling speed.
On my custom board, when i use the multiplier of 2, the leds toggle and everything works on 8MHz (as per SystemClock on debug)
When i use the multiplier of 3, it gives me 12MHz.
When i look at the SystemCoreClockUpdate() routine on my custom board, RCC->CFGR & RCC_CFGR_SWS does not give me 0x08. So PLL isn't used as system clock.
This is only when the multiplier is 2 or 3, else it resets and i cannot debug the chip.
The moment i use a multiplier of 4 and up, the chip does nothing and attached you can see the nRST pin.. So it cycles the reset line.
The schematic in attachment also.
Greetings
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