SAMC with PLL frequency drift with temperature

[Simon]

right so my 25ppm 0.04ppm/C^2 is not so bad after all. All I need is to do CAN bus communication. This requires a clock stability of 1%, that is 10'000ppm.

I can't say for sure that the chip was running from the internal RC oscillator but Ataradov's assessment of my code is pretty conclusive and the reaction of the chips to temperature very telling of an RC oscillator. When work have finished politicking for their boss from the US I can get down to some further testing which is worth it because it will salvage this first machine for further demo work while I work on the newer version.