I have main entity for example.
I also have RAM 16*8bit component. Which has port (address, accessing indicator, reading indicator, writing indicator, IN/OUT DATA)
So, first 16 clock cycles I need to read main's entity input (byte_input). And send it to RAM component.
From 16 to 32 clock cycles, I have to read data from RAM, process it and rewrite again to ram component from 32 to 48 clock cycles.
But I stalled in the first part. I can't even read entity's input and send it to the RAM. When synthesizing it says "Multi-source in Unit <top_module> on signal <ram_data<2>>; this signal is connected to multiple drivers"
![Embarrassed :-[](https://www.eevblog.com/forum/Smileys/default/xembarrassed.gif.pagespeed.ic.zcm3EmNu9T.png)
Code:
PROCESS(clk)
BEGIN
if(rising_edge(Clk)) then
if (cnt>=0 and cnt<16) then
ram_data<=byte_input;
end if;
end if;
end process;
gate_1: ram16x8 port map(address=>ram_address,csbar=>'0',oebar=>'0',webar=>ram_webar,data=>ram_data);
![](http://www.imageup.ru/img220/1753877/error.png)