I don’t have the time to enter, but I have been thinking about the low noise target.
TiN’s initial benchmark is 120nV pk-pk over 0.1-10Hz.
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Thought A: low frequency chopper
Estimate RMS noise = pk-pk / 6.6, we get 18nV RMS
Equivalent noise BW = 1.6 * 10 = 16 Hz
Allowable noise: 18/sqrt(16) = 4.5nV / sqrt(Hz)
For low input current, use something like TI JFE2140 for first gain stage (1.4nV /sqrt(Hz) for pair and 20pA Ibias). Chopper frequency would need to be low to keep the switched capacitor current low.
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Thought B: direct amplifier
JFE2140 rated for 120nV pk-pk typical over 0.1-10Hz. (At id = 2mA, gm=10mA/V.) Part binning might be required.
But there are 2 in a diff amp, so multiply by sqrt(2). That takes us over limit, so parallel 3 stages for 120*sqrt(2/3) = approx 100nV
That leaves us some 66 nV pk-pk or 10 nV/sqrt(Hz) for everything else.
Estimate RMS noise = pk-pk / 6.6, we get 10nV RMS.
Equivalent noise BW = 1.6 * 10 = 16 Hz
Allowable noise: 10/sqrt(16) = 2.5nV / sqrt(Hz)
Assuming around 150 R (1.55nV/rtHz) for input protection (and matching feedback divider) leaves 1.2nV/rtHz for everything else, referred to input.
Given gm = 30mA/V, a 1k drain resistor and differential signal collection I think the JFET stage would have a gain of around 60V/V. Being pessimistic I’ll halve that to 30V/V. Therefore the 1.2nV/rtHz coverts to 36nV/rtHz after JFET gain. Now to see what I can get in the way of opamps… the opamp 1/f noise could be an issue.
A big factor to consider is the temperature drift below 0.1Hz. Has anyone tried ovenized JFETs before for constant temperature? I was thinking a 45 deg C oven might work, and one could put the voltage reference in there too.