DMTD board

[tkamiya]

Yes, I did.

A 3 terminal regulator on -5V rail was wired incorrectly.  The power supply was working well when I tested individually.  I must have messed it up when I noticed it was getting quite hot that I removed it from PCB and mounted it on bottom of the case.  Once I corrected the wiring, it settled down to where it should be.  I knew negative regulators are oddball when it comes to pin out, so I was being careful, I thought....

[Mrt12]

I did some first tests with my DMTD board. I connected 10 MHz to one input and 9.99999 MHz to the other input. At the output, I got a nice 5V TTL signal with 10 Hz. I measured the frequency with my HP 5372 timing analyzer. I saw that this frequency was jumping up and down by around 0.0001 Hz. However, I had locked my two signal generators to the same external 10 MHz reference... so I am unsure why I do have this instability. Can it mean that my signal generators are indeed that bad or does it perhaps mean that my circuit is unstable?

If I am correct, this 100 uHz instability translates to 1e-12 instability at 10 MHz at tau=0.1 sec. Is that right?

Further, another interesting question: If I want to compare two oscillators having the same nominal frequency, say 10 MHz. Then I use an offset oscillator which is, say, 10 Hz higher.
However the offset oscillator is maybe not 100% accurately 10 Hz high, so the beat note at the output will perhaps be something like 9.999 Hz or 10.001 Hz. So my tau is not actually 0.1 second, but merely something like 0.10001s or 0.09999s. Does that matter when I want to make an ADEV plot? or can I neglect this tiny error and say this is exactly 0.1s?

[notfaded1]

Yes, I did.

A 3 terminal regulator on -5V rail was wired incorrectly.  The power supply was working well when I tested individually.  I must have messed it up when I noticed it was getting quite hot that I removed it from PCB and mounted it on bottom of the case.  Once I corrected the wiring, it settled down to where it should be.  I knew negative regulators are oddball when it comes to pin out, so I was being careful, I thought....

Taka-

This is exactly where I'm at now trying to figure out the power supply and voltage regulators.  I ordered and received some of long SMA jacks and also got some SMA to Female BNC headers so I could use BNC on the output if I want or stick to SMA.  The  power supplies I got are POWER ONE HTAA-16W-AG linear power supplies.  I got two for a good deal.  It seems the negative voltage regulators can have a real need for a heatsink from what everyone has told me?  Are the negative really any different from the positive if either would be 12V to 5V with LM340T-5.0 vs. LM320T-5.0?  As, you said Taka I also noticed the pinouts are different between the LM340 and LM320.  Also I've noticed people usually put an electrolytic capacitor across the input and output and sometimes also a small ceramic as well on the output around the linear voltage regulator.  What size caps would you suggest I use with 12V to 5V on both sides?

Bill

[tkamiya]

Hi, Bill!

First, the connectors and internal wiring.  I avoided using flexible coax.  On front panel, there are N to sma panel mount adapter.  From there, semi-rigid connector goes to the PCB.  I've noticed there is a lot of noise picked up on output cable.  I suspect ground loop of some kind.  I'm in process of insulating output connector.

On 3 terminal regulators, I used 0.1uF on back side of PCB to reduce inductance, and on front, 10uF aluminum caps.  I've always done it that way.  On 5V negative side,the regulator actually does get hot.  I mounted on bottom of the case.  0.1uF right at the regulator, short piece of wire, and 10uF on PCB.  The reason I use both is that some brand of 3 terminal regulators are prone to oscillation at high frequency where regular aluminum caps are not that effective.

If you look at spec sheet for those regulators, they typically suggest 0.1uf and 1uf.  Somewhere else on the note, those are for tantalum and use of aluminum requires x10 the value.  I just go by my past experience and do what I said above.

My regulators are just typical 78 and 79 series.  I did not use anything special.

For filter caps, I used as large as I could find.  I recall each leg has 6800uF or something like that.  Then, I put two ferrite beads on output - although it does not appear they did anything meaningful.

[tkamiya]

This is something I do and certainly not a universal practice.

I don't trust BNC.  It is because NOT all BNCs are bad, bu there are SO MANY substandard BNC around.  I try to avoid them as much as I can.  I use N mostly.  SMB has 300 connect/disconnect limit.  Fine for internal connections.  I don't know about external ones unless you use connector savers.

[tkamiya]

Oh, by the way....

I noticed there were LOTS of noise generated SOMEWHERE in my lab.  Perhaps it's from LED lighting overhead.  Perhaps all the test equipment in the room, or even dozens of 10MHz sources in the lab.  Something to think about when you are testing yours.  Ultimately, I plan to put everything on custom made 19" aluminum rack, battery powered, and do particularly sensitive measurement outside my main lab and computer room.  USB connection will be via fiber optic.  Perhaps this is over-the-top.  But I've spent enough time looking for noise sources, I learned to not assume anything.

[Mrt12]

Hi guys

I have attached a first proper measurement I made.
I used a 5 MHz FTS1000 as external reference for my HP 8663A signal generator and set the signal generator output frequency to 4.99999 MHz. This produces a 10 Hz beat note at my DMTD output. I measured this frequency with a HP 5335A counter and let TimeLab read the data from the counter via GPIB.
The resulting plot is in the attachment.

a) is it right - I have to scale the whole thing by 10Hz/5MHz = 2e-6? so my stability at 1sec would be around 2e-12?
b) doesn't look terribly good, does it? I guess the HP 8663A is adding a bit of noise, but THAT MUCH?

I am still waiting for some parts so I could not yet make a proper DMTD measurement - still only one channel is fully populated with all ICs :-/

[tkamiya]

You are getting the same problem I did.  That's not right at all.  You should be getting -12 at least.

Instead of recording and graphing at the same time, record it in terminal software first, then feed it to TimeLab.  When I did that, factors were interpreted correctly.  I don't know why that made a difference but it did.

[Mrt12]

Hi Taka
Indeed, TimeLab seems to have a problem with the scaling factor!
For some reason it is correct now. Instead of Frequency measurement, I did period measurement. And for this, the scaling factor works fine!

Interesting: I did a test where I compared a FTS1000 against HP 8663A, and a SLCR-101 (Rb) against HP 8663A. The Rb is more than 10 times worse, but the numbers seem to be in the right order of magnitude: http://www.ke5fx.com/rb.htm

I also tested a HP 33120A function generator and the curve looks sort of good to me - kind of what I expect.
However the numbers for the FTS1000 are much TOO good to believe!

Anyways, I think I am on the right track now! as soon as I have all remaining missing ICs ready I can go for the proper DMTD or dual DMTD and even do cross correlation.

[tkamiya]

Oh, wait!  Did you say you have only one channel completed?  That's why.  You don't have the start>stop time interval, yet. 

I'm doing A-B TI (A->B) (time interval).  Yet, if I set it that way, and do simultaneous measurement, Adev starts from E-7 and goes down from there.  (set up as multiplication factor E-7) I also noticed odd waving motion and abrupt start.  All of that is gone if I record it first and import the data.  I'm running 24 hour test, so I cannot interrupt it.  But I'll have to figure this out.  I doubt TimeLab has a bug like this with so many users involved in testing and using.  I think I'm doing something wrong.  It works with TICC but from HP53132, TimeLab stopped displaying anything.  Yet, from terminal emulator, I see valid data.

I have a big plan for this setup, so I need each piece done correctly and tested. 

By the way, I'm using TAPR TICC but someone has also made a simpler and less expensive version.  I've seen it somewhere.  That may be all we need.  All these digits are mainly wasted anyway.

Have you tested by changing difference oscillator from crystal to HP8663A?  I'm still not clear on how good this diff osc needs to be and how much it affects the result.

[Mrt12]

Taka,
yes, I have only one channel at the moment as I am missing some OpAmps and comparators.
But I think the single-mixer heterodyne technique still should work - I can measure the output frequency or period of the resulting mixing product....
Anyways, I guess tomorrow I will get the missing parts. We'll see how it works ;-)

what is your big plan you have for this device?


Indeed it is not yet very clear how good the difference oscillator needs to be, but from what we can read from Bill Riley the difference oscillator should cancel out IF the zero crossings are CLOSE TOGETHER.
However if a beat note of 10 Hz is used, the zero crossings can be at max. 100ms apart, so I assume the ADEV of the difference oscillator at 100ms is a limiting factor, but I am not sure how much it affects the measurement.

[KE5FX]

You are getting the same problem I did.  That's not right at all.  You should be getting -12 at least.

Instead of recording and graphing at the same time, record it in terminal software first, then feed it to TimeLab.  When I did that, factors were interpreted correctly.  I don't know why that made a difference but it did.

Thanks for the heads-up on this, will take a look. 

[tkamiya]

John,
I was going to retest this and send you a more formal report.  But what I said was what I saw.  Thanks for looking into it.

MRT12
Yes, I was told of this technique, single mixer setup a while back.  It just won't have "cancel out" feature of double setup.  I know if one chooses too narrow of offset and relationship between f1 and f2 changes, then it will return an invalid response.  I am not sure if zero crossing point makes difference.  That happens at mixer stage.

My plan is to expand this to 4 channel minimum, hopefully 8 channel.  Set everything up in one short rack, except for PC and operate it under battery.  Connection between PC and TIC will be an optical fiber.  Earlier in testing, I was amazed how much noise a short piece of coax between counter and DMTD picks up.  I was using good quality TMR240(Times something brand?) coax, too.  Also, isolation between the case and ground side of coax appears to make some difference as well.  So by going all-in-one route, I intend to eliminate as much variable as possible.  I'm hoping I can pick up some more resolution, too.  Still too early in stages to say for sure, but looks like Corby's design has quite a bit more potential than we are seeing right now.

[Mrt12]

Taka,

Still too early in stages to say for sure, but looks like Corby's design has quite a bit more potential than we are seeing right now.

I agree BUT we also shall be a bit cautious: I don't know if you use Corby's original variant with the MC1650 comparator or my variant with the MC100EL16 gate.
For the former, the jitter of the MC1650 is not specified, but for the MC100EL16 a typical jitter of 0.7ps is specified - that's 0.7e-12, I am not sure whether this also scales with 1e-6 - in that case it would be totally fine - or whether it stays like so - in this case the noise floor would be somewhat limited. The MC100EP16 would be the better choice then (0.2ps).
I doubt that the very dated MC1650 are much better than that, so I wonder what limitations arise from this.


Can somebody maybe explain how the jitter of the ECL gate scales when the heterodyning occurs?

[thinkfat]

Taka,

Still too early in stages to say for sure, but looks like Corby's design has quite a bit more potential than we are seeing right now.

I agree BUT we also shall be a bit cautious: I don't know if you use Corby's original variant with the MC1650 comparator or my variant with the MC100EL16 gate.
For the former, the jitter of the MC1650 is not specified, but for the MC100EL16 a typical jitter of 0.7ps is specified - that's 0.7e-12, I am not sure whether this also scales with 1e-6 - in that case it would be totally fine - or whether it stays like so - in this case the noise floor would be somewhat limited. The MC100EP16 would be the better choice then (0.2ps).
I doubt that the very dated MC1650 are much better than that, so I wonder what limitations arise from this.


Can somebody maybe explain how the jitter of the ECL gate scales when the heterodyning occurs?

The jitter will add to the jitter of your source. It's in the same domain (RF), before the mixer stage.

[Mrt12]

The jitter will add to the jitter of your source. It's in the same domain (RF), before the mixer stage.

sure. So that means it is also divided by the heterodyne factor?

[tkamiya]

That's what I was thinking.  Anything before mixer will be RF.  That gets hetrodyned to 1Hz after the mixer so the "dividing effect" takes place.  I think the exception is the offset oscillator signal.  Since they both get applied equally, it isn't critical.  At least that's my understanding.  I really would like a final word on this but so far, I haven't found any material indicating one way or another.

Then...  I wonder if ECL jitter is critical?  I'm thinking if they are from same batch, it may behave similarly enough that end result may be close enough.

[Mrt12]

I think even if the ECL gates are from the same batch, their jitter won't be equal as jitter is a random process.
But I think it is indeed the case that the jitter is in the RF domain and heterodyned down, which means that the 0.7ps Jitter yields a jitter of 0.7e-18 noise floor. So nothing to worry about.

[Gerhard_dk4xp]

> I think the exception is the offset oscillator signal.  Since they
> both get applied equally, it isn't critical.  At least that's my
> understanding.  I really would like a final word on this but so far,
> I haven't found any material indicating one way or another.

The noise of the downconversion oscillator won't cancel completely.

That's for the letters TD in DMTD. The two channels are evaluated at
different times, so they get at least somewhat different noise.

Cheers, Gerhard

[tkamiya]

Right.  But time interval is short enough the amount of drift/jitter should be very very small.  I think that was the point Corby was trying to show us by having DUT and reference pulse as close as possible.

[5065AGuru]

Hi,

Here is more data on how the quality of the offset oscillator affects the performance and also
another illustration of the importance of keeping close to coincidence.
I took a well performing oscillator and injected calibrated amounts of noise and measured
how much the STS was degraded by several fixed amounts.

AD at 1Sec for indicated noise levels
 
8.65X10-13th          Zero
3.10X10-12th          62.5
5.66X10-12th          125
9.72X10-12th          250
1.36X10-11th          375
2.26X10-11th          500

Then I setup to measure the simple dual mixer noise floor with this oscillator as the offset
oscillator.

I measured the noise floor at close to coincidence and also at close to full scale at the 6
levels of noise shown.

The plot shows all 12 300 Sec. measurements with the 6 close to coincidence on the left.
As you can see close to coincidence the noise floor stays fairly constant at all noise levels.
At the midpoint we transition to the 6 close to full scale measurements.
With no noise the first section is not too bad but as the noise is increased you can clearly
see the noise levels rise up.

This should help you select what oscillator to use as your offset oscillator.

I'm currently running some oscillator to oscillator plots with the 6 noise levels and will
post those results soon.

Cheers,

Corby

[Mrt12]

Corby,

I don't understand all of your post. STS? what's that?

Also I cannot yet interpret your chart correctly. Could you again please explain (for the dummies) what the x and y axes are? 

But I guess if the DMTD is adjusted such that the zero crossings are very very close together, the noise of the offset oscillator really cancels out well. There was once a discussion in the time-nuts with Ulrich Bangert about this topic, and he also said that, if the zero crossings are "far" apart, the offset oscillator will change its state in the meantime and therefore it cannot cancel out perfectly.

[5065AGuru]

Mrt12,

STS is "short term stability"

The X axis is in Seconds.

The Y axis is not calibrated as I just wanted to show relative noise levels.

Yes it cancels out well when close, that's what I'm trying to show as well as what the noise level of your offset oscillator does to affect performance.

Here is another plot that shows the AD degradation as the offset oscillator noise increases, all plots close to coincidence.

Cheers,

Corby

[tkamiya]

I'm making a PCB design for HP10811.  Should be handy for offset or reference oscillator.  I'll post here when it's done.

[Mrt12]

Sorry I was wrong yesterday, of course the jitter of the ECL gates is multiplied by the heterodyne factor!

@Corby. Do you have an idea how large the jitter of your MC1650 comparators is?
you said you measured the noise floor of your DMTD and that was quite good, but I wonder how big the ECL jitter contribution is. 0.7ps yiels 0.7e-6 when heterodyned with 10^6, that's quite a lot. On the other hand I can't imagine that your very old MC1650 has much better jitter performance - but as far as I remember you had noise levels in the 1e-13 range, I don't understand yet how that is possible.

The best ECL gates I found do have a jitter of 0.2ps, that would still be 0.2e-6.

Maybe the thing is that this jitter is PER PERIOD and since we are prodicing a 10 Hz beat note the jitter is averaged over 100ms and thus becomes lower?

by the way thanks for your explanations!