I know that FR4 has quite some loss, compared to low loss dielectrics. However the good thing is that there is not much field in parallel to the capacitor. The integrator input is a virtual ground and largely surrounded by guards. The other capacitor side is kind of avoiding close neighborhood . I could check the effect of the board by testing with 2 caps in parallel - this should reduce the relative effect of the board or other parasitic capacitance.
I don't think I would need Teflon standoffs at the ADC. There should be reasonable low leakage, but in my version with reading the residual charge at a fixed time, leakage is only a 2 nd order problem. The switch chip is not really specified for low leakage anyway - in the current setup I still get an effective bias current to the integrator in the 5-10 pA range - so must be some luck there. As am still doing quite some changes I have not even cleaned the flux (no clean type).
I still have a few C0G types caps to test. From a quick look at the data-sheets something like Vishay VJ0805D102KXAAJ (1 nF) , a low loss 0805 cap is my current favorite. They are specified for >100 GOhms and < 0.05% dissipation at 1 MHz or 1 kHz (for 1.5 nF).
To avoid the small, hard to clean area under the chip, I consider mounting the cap upright standing with an extra bodge wire.
The Bob Pease article on DA has a nice graph. My measurements contain data for some 30 ms of charge, some 2 ms effective discharge (use this time as zero point) and 20 ms recovery. So I can show the approximate data on the graph. The red circle is for the PP caps and THT NP0, the green is about the SMD NP0 (Vishay VJ1206A...) and yellow is the PS cap. The graph is a little confusing in using the discharge time for the scale.