I run single 1.8V for VCCIO and VCCBRAM, AUX etc everything for most 16nm/28nm FPGA like xilinx, efinix etc
This means I have only two power planes to deal with Vddcore and 1.8V.. IE no 3.3V. Those go in the upper 4 layers (TOP, Vcore, GND, Vio ) and I dont need any caps on the bottom side...nor does the fpga have to reach down below the FR4 core to the bottom 4 layers for power....
On 7 series though, 2.5V LVDS output, yes, need the extra small platelette. You can run them down to about 2.35V and they still make spec at full gas over temp. datasheet says 2.375V. It is worth it because you can save quite a bit of heat.
1.8V LVDS compared ot 2.5 in xilinx is about 1/3 the power from memory......
anyway, yeah Renases , bit of a mystery there. It's an interesting year for FPGA because you have Lattice AVANT E, Altera Agilex5, and new SERDES RISCV hardcore Efinix all being production available by year end.
new Xilinx Spartan 8 is interesting for some (lots of 3.3V IO) but lacks 1.8V IO (quantity) for me.