Ok, only a minor error:
Line 60:
.INPUT_CLK_HZ (
CMD_CLK_HZ ),
Change to: CLK_IN_HZ
The parameter 'CMD_CLK_HZ' is outside this module feeding this module's parameter 'CLK_IN_HZ'.
Line 61:
.OUTPUT_CLK_HZ (
(48000*64) ), // 48KHz signal
Change to: CLK_I2S_HZ.
You may place the '(48000*64)' in place of the '3072000' on parameter line 5.
Or, even better, rename parameter on line 5 from 'CLK_I2S_HZ' to 'I2S_DAC_HZ' and just place 48000 there.
Then on line 61, change it's output clock setting to this:
.OUTPUT_CLK_HZ ( I2S_DAC_HZ*64 ), // 48KHz signal
We don't need line 27, that is specifically for the _tb.sv module and its simulated master clock.
That's it. You did very well.
If I understand it all correctly, I'm going to need a 16-bit output to the I2S transmitter, which means DAC_BITS can only be 15, unless I add in some code to automatically 'make up' the width to 16 bits no matter what DAC_BITS value is entered - is that right?
The 'DAC_BITS' (currently set to 10) now defines the depth of each channel's, A-B-C audio output.
When mixing/adding the 3 together, we then need at least 12 bits for the mixed sound output.
As I told you earlier, the I2S transmitter can operate anywhere between 8 bits and 32 bits in, so for the way the system is currently setup, the PSG's output is feeding 12bit audio through the I2S TX.
Remember the second half of what you missed to acknowledge here:
Now, say we want 3 dacs in our system, a cheap 16 bit one with a headphone output and a 20 bit line level one and 24 bit for the HDMI, all with the same sound. Notice how the MSB is at the beginning. What would happen if we feed all 3 digital sources the same signal, all expecting 32 clocks per channel, but each outputting the most bits they can?
Ah of course, yes, I understand. ![ThumbsUp :-+](https://www.eevblog.com/forum/Smileys/default/icon_smile_thumbsup.gif.pagespeed.ce._JElyJQqdB.gif)
The paragraph right after that one I wrote:
Also, look at it the other way around, say we can only generate 8 bit audio, meaning after our 8th bit lsb, we just send a bunch of blank zeros until the 32nd clock when the right channel begins and we send it's msb? Will all 3 dacs on our bus still work OK?
So setting the I2S DAC_BITS to 12 bits is the correct action and it will just shove the 12 data bits from the left and right inputs all the way up to the left-most on the output, and if the DAC's is actually a 16bit one, it will just receive a bunch of zeroes for it's LSBs.
That should do it for your 'arya_top'. Once you placed it in your GPU and verify that it sounds ok, next place it in your 'jt49_tb.sv', replacing lines 28 through 151 and polish the setup_psg.do. Upload everything here and I will make my own new proper output stereo mixer and filter module from scratch, then we will close up this part of the project.
QUESTION: Why did you call it '
arya_top', what does 'arya' stand for?
Keep in mind that after we finish the filter, we will Github publish this customized fork of jt49's original. Maybe you should more carefully think about the name.
Too bad you didn't want to do this the right way. You could have had a 16-64 voice stereo HD audio experience with full stereo sampled instruments held in DDR3. Anyways... The stereo 8 channel YM2151 would have been a much nicer PSG.