Well, it seems to simulate for me.
Though, as you can see, I decomposed your command input so I can read what command I'm sending:
![FPGA VGA Controller for 8-bit computer](https://www.eevblog.com/forum/index.php?action=dlattach;topic=214604.0;attach=1040798;image)
Now, when simulating, as you can see, the read_req_a is sent out, but, it stays on indefinitely and has a delay:
![FPGA VGA Controller for 8-bit computer](https://www.eevblog.com/forum/index.php?action=dlattach;topic=214604.0;attach=1040802;image)
Now, as you can see, I've added output pins to tap the memory and read rdy flags.
In the attached .zip, I've also added the 'SDC1.sdc' file to tell Quartus that we need the design to at least function at 125MHz so the timing report will be accurate instead of all red.
In the simulation, I've changed your clock to 100MHz exact so it is easy to read and edit the stimulus inputs.
Your next task is to fix the logic of the 'read_req_a' so it has 0 delay and stays on only for 1 clock.
Oh, BTW, did I ever say we needed a 'next_cmd' output? I don't remember.
Get rid of it unless for now you tie it to 'exec_cmd' just to see what it's doing.