![Phew :phew:](https://www.eevblog.com/forum/Smileys/default/phew.gif.pagespeed.ce.n2uLOVFYMP.gif)
Here's the PCB design - all manually routed. I must admit, there's a certain sense of achievement in doing it yourself - plus much finer control over trace widths for power supplies etc. ![ThumbsUp :-+](https://www.eevblog.com/forum/Smileys/default/icon_smile_thumbsup.gif.pagespeed.ce._JElyJQqdB.gif)
I get the feeling I've learned a lot from this exercise. ![Grin ;D](https://www.eevblog.com/forum/Smileys/default/xgrin.gif.pagespeed.ic.QVVz6XIT20.png)
![Indifferent :=\](https://www.eevblog.com/forum/Smileys/default/indifferent0023.gif)
Nice.
![ThumbsUp :-+](https://www.eevblog.com/forum/Smileys/default/icon_smile_thumbsup.gif.pagespeed.ce._JElyJQqdB.gif)
Amazing job for a first timer!!!
Now, I understand the difficulty in achieving this 2 layer design with all the limitations. Since I cant see net names, I only see 2 little things to consider.
FB4 is receiving power through a trace going through an IC pads and vias. I'm not sure about the bottom cap next to how C10 is wired. Try removing the FB3 and FB4 from your schematic. You will simplify a few GND connections and remove a few caps in your design that way maybe allowing a better path for FB4's Vpll.
Hang on a sec, something seems wrong with the Vpll and VCCint, are some of those shorted, or, on the wrong pins?
Can you show me a printout/screenshot with net names on the FPGA pins?
As well as net names on the other components?