A Verilog I2C initializer with integrated RS232 debugger

[Wiljan]

Ok Wiljan, here is my beta v1.1.

New:
I renamed my source to: BHG_I2C_init_RS232_debugger.sv
On line 2, I added this commented out define:

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//`define  USE_SEPARATE_DIN_DOUT_OE        // Enable this line ti use separate I2C_scl/sda_din/dout/oe IO ports.
Enable this define and get 2 input ports and 4 output ports to directly drive your Efinix's dumb IO buffer.

There are 2 new parameters:

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      parameter bit        CLK_STRETCH      = 0       , // 0=High speed, 1=wait for slave to release the I2C_clk line.
      parameter bit        CLK_STRETCH_ALL  = 0       , // 0=wait for slave only during the ACK, 1=wait for slave every clock cycle.
For now, I am only using the 'CLK_STRETCH' and it should wait at every rise of the clock to see if the slave is ready before continuing.

Let me know what this does and do a close scope inspection to verify that I didn't accidentally drive the clock low for an instant after detecting the rise.  This has to do with the OE timing and I need to see if I need to add an extra delay before or after toggling the OE and reading the IO as an input.

THX.

I have tested v1.1 and it does work 
Had to turn on:

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`define  USE_SEPARATE_DIN_DOUT_OE
TRI_I2C_scl      = 1
CLK_STRETCH      = 1

And add in some parameter to send data. First I just tried with the "8A 80 00" and "8A 85 00" with CLK_Stretch=0  and then with CLK_Stretch=1 and you see a clear difference on the scope

Then I added in the data needed for the RPI display and you see a long low clock you also a clk with half level on STOP condition on all the Scope grabs

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`ifdef ENABLE_RS232_EDITOR
`include "sync_rs232_uart.v" // Include the sync_rs232_uart.v source only if the ENABLE_RS232_EDITOR feature is enabled.
`endif

module BHG_I2C_init_RS232_debugger #(

      parameter            CLK_IN_KHZ       = 25000   , // Source  clk_in  frequency in KHz, typically at least 8x the desired I2C rate.  Recommend 25000-100000KHz.
      parameter            I2C_KHZ          = 100     , // Desired clk_out frequency in KHz, use 100, 400, or 1000.
      parameter            RS232_BAUD       = 115260  , // Desired RS232 baud rate.
      parameter bit        TRI_I2C_scl      = 1       , // 0=I2C_scl & data output is tri-stated when inactive. 1=I2C_scl is always output enabled.
      parameter bit        CLK_STRETCH      = 1       , // 0=High speed, 1=wait for slave to release the I2C_clk line.
      parameter bit        CLK_STRETCH_ALL  = 0       , // 0=wait for slave only during the ACK, 1=wait for slave every clock cycle.

      parameter            TX_TABLE_len                     = 14,              // Number of entries in table.
      parameter bit [16:0] TX_TABLE_data [0:TX_TABLE_len-1] = '{
      // PRI 7" LCD init
      17'h1_0101,  //  1 Set rst_out high.
      17'h1_0100,  //  2 Set rst_out low.
      17'h1_008A,  //  3 I2C address 0x45
      17'h0_8000,  //  4 Reg 0x80 = 0x00
      17'h1_0204,  //  5 delay
      17'h0_8500,  //  6 Reg 0x85 = 0x00 Power 01 = on  00 = off
      17'h1_0204,  //  7 delay
      17'h0_8501,  //  8 Reg 0x85 = 0x01 Power 01 = on  00 = off
      17'h1_0204,  //  9 delay
      17'h0_8108,  // 10 Reg 0x81 = 0x08  Orientation 0x08 = landscape 0x04 = portrait
      17'h1_0204,  // 11 delay
      17'h0_8600,  // 12 Reg 0x86 = 0x00  Backlight 0 = 0% FF = 100%
      17'h1_0204,  // 13 delay
      17'h0_86ff   // 14 Reg 0x86 = 0xFF  Backlight 0 = 0% FF = 100%
      } // Contents of table.
   
The RPI Dipslay does turn ON now 

I then have to look into the LS init over DSI but that's something very different.

Brian let me know if you want me to test something specific, thank you lot for the quick help 

[BrianHG]

Hi Wiljan,
     If you look at my attached photo from your scope shot, you will see I also needed to do a 'clock stretch' before sending the 'I2C stop'.  This is probably required in case we send multiple bytes in succession, the slave might still be busy, not see a stop, or it wont be ready to see the 'I2C Start' at the next transaction.

I attached beta 1.1b.  I also removed the 'CLK_STRETCH_ALL' parameter as the FPGA sees the pullup so fast checking at each clk rise, the bitrate loss is inconsequential.

Please provide new scope shots so I can see if I cleaned up the 'I2C Stop' bus contention.

Wiljan, if you could also do me the favor of do a recapture zooming (time/horizontal) into one of the clk rises so I can see if it doesn't stutter during that tiny partial step.

[Wiljan]

Hi Wiljan,
     If you look at my attached photo from your scope shot, you will see I also needed to do a 'clock stretch' before sending the 'I2C stop'.

Yeah I saw that and did mention it in my last reply, guess the mcu are busy in processing the command. Sure a clk check will be correct before the Stop is send.

If you look on block 3 send the "8A 85 01" you will see the ACK fails, not sure why there is a long low clk just before, was also in 1.1 (the LCD does not turn on)
The low was there in 1.1 (I expect the mcu is doing it), I guess if I add in some delay it will work.

[Wiljan]

Added in some delay and it works LCD is on

Code: [Select]

      parameter            TX_TABLE_len                     = 14,              // Number of entries in table.
      parameter bit [16:0] TX_TABLE_data [0:TX_TABLE_len-1] = '{
      // PRI 7" LCD init
      17'h1_0101,  //  1 Set rst_out high.
      17'h1_0100,  //  2 Set rst_out low.
      17'h1_008A,  //  3 I2C address 0x45
      17'h0_8000,  //  4 Reg 0x80 = 0x00
      17'h1_0201,  //  5 delay
      17'h0_8500,  //  6 Reg 0x85 = 0x00 Power 01 = on  00 = off
      17'h1_0220,  //  7 delay
      17'h0_8501,  //  8 Reg 0x85 = 0x01 Power 01 = on  00 = off
      17'h1_0220,  //  9 delay
      17'h0_8108,  // 10 Reg 0x81 = 0x08  Orientation 0x08 = landscape 0x04 = portrait
      17'h1_0201,  // 11 delay
      17'h0_8600,  // 12 Reg 0x86 = 0x00  Backlight 0 = 0% FF = 100%
      17'h1_0201,  // 13 delay
      17'h0_86ff   // 14 Reg 0x86 = 0xFF  Backlight 0 = 0% FF = 100%
      } // Contents of table.


[BrianHG]

Added in some delay and it works LCD is on

Yup, that's why I wrote this I2C initializer.  I had TI audio codecs on my dev board.  They require multiple reset and delays until the next command, plus a string of settings just to get them to play a sound.

As you can see, the two checks check out.  I will update my GitHub and this page with the v1.1 release later today.

[Wiljan]

Yup, that's why I wrote this I2C initializer.  I had TI audio codecs on my dev board.  They require multiple reset and delays until the next command, plus a string of settings just to get them to play a sound.

As you can see, the two checks check out.  I will update my GitHub and this page with the v1.1 release later today.

Yeah all is fine , Thank you Brian

[BrianHG]

Official v1.1 release:
***************************************************************************
New v1.1.
BHG_I2C_init_RS232_debugger.sv & testbench  V1.1, June 2023.
----------------------------------------------------------------------------------------------------
New v1.1 Features: Supports I2C CLK stretch.

   - Changes the source file from a .v to a .sv for better compiler compatibility.
   - Added parameters CLK_STRETCH. Enable with TRI_I2C_scl to properly support the feature.
   - Added on line 2, an optional `define USE_SEPARATE_DIN_DOUT_OE, which changes the I2C bus from 2x INOUTs to 6 ports, SCL/SDA _in, _out, _oe for manually driving Efinix's IO primitive.

See top of thread or GitHub for new source files:
bhg_i2c_init_rs232_debugger-an-i2c-initializer-with-integrated-rs232-debugger/
https://github.com/BrianHGinc/BHG_I2C_init_RS232_debugger