Based on what I understand from the datasheets, once an FPGA signals that it has completed its configuration, it then cascades control to another FPGA (if it were to exist) via the nCEO pin.
In such a situation, the data and clock signals (which are paralleled between all devices to be configured) would continue to pulse, but any FPGAs that have asserted their nCEO pins should no longer be observing them.
So as long as you don't take nCONFIG low to initiate configuration again, it should be fine to do what ever you want with the data and clock pins after configuration is complete.
Someone else could hopefully double check that this is correct.