Access BRAM linearly

[zer0c00l]

I have defined some BRAM in FPGA where each entry is 32bits, and the depth is 8192. Each entry will store 8 (4bit )numbers (8x4bits = 32bits). I can access BRAM starting at address 0 and increment the address by 4 (word addressing). After reading 32 bits I just split it into 4 bits each to get the stored number. How can I access the stored numbers linearly.
Lets assume that the number stored at address 0, bits [31:28] is 1, bits [27:24] is 2 and so on. If I want to access the number stored at location 70 which would be at address 32, bits [15:12]. How can I do that?. The algorithm I am trying to implement will generate location 70, and I need to convert location 70 into BRAM address and bit location

[ataradov]

Something like this will work:

Code: [Select]

wire [15:0] nibble_address; // Your location 70
wire [12:0] word_address = nibble_address[15:3];
wire [2:0] nibble_index = nibble_address[2:0];
wire [4:0] bit_location = { nibble_index, 2'b00 };


[zer0c00l]

Something like this will work:

Code: [Select]

wire [15:0] nibble_address; // Your location 70
wire [12:0] word_address = nibble_address[15:3];
wire [2:0] nibble_index = nibble_address[2:0];
wire [4:0] bit_location = { nibble_index, 2'b00 };


70 in binary would be 1000110 (nibble_address = 1000110)


wire [12:0] word_address = nibble_address[15:3];
This would make word_address = 8 (nibble_address[15:3] = 0000000000001000)

but 70 would be stored in word_address 32

Please see attached image

[ataradov]

It will be byte address 32 and word address 8. If your BRAM is configured as a 32-bit wide RAM, then you need to supply 8, not 32 as an address.

[zer0c00l]

But how can location 70 be at address 8?. If each location is of 4bits then word address 0 will have locations 1 to 8, word address 1 will have locations 9 to 16, and word address 8 will have locations 17 to 24

[ataradov]

Word address 0 will have locations 0 to 7. Word address N will have locations N*8 - N*8+7. So word address 8 will have locations 64-71.

PS: Numbering things from "1" will not get you very far in a digital world. You can have any logical meaning assigned to the addresses, but on a low level you should always number things from 0.

[NorthGuy]

Wouldn't it be easier for you to configure BRAM as 4-bit wide instead of 32-bit wide?

[asmi]

I would recommend at first to use inference instead of instantiation as it's more flexible and it makes code more readable (remember the code is written once, but read many-many times, so it's very important to make it as readable as possible). It would also help to be aware of BRAM limitations - like very large clock-to-out time unless output pipeline register is used. The same is generally applicable to most hard IPs inside FPGA as routing delays to and from such blocks tend to be quite high. There is a reason why FPGA vendors tend to include a crap ton of pipeline registers in such blocks.

[zer0c00l]

Wouldn't it be easier for you to configure BRAM as 4-bit wide instead of 32-bit wide?

I would recommend at first to use inference instead of instantiation as it's more flexible and it makes code more readable (remember the code is written once, but read many-many times, so it's very important to make it as readable as possible). It would also help to be aware of BRAM limitations - like very large clock-to-out time unless output pipeline register is used. The same is generally applicable to most hard IPs inside FPGA as routing delays to and from such blocks tend to be quite high. There is a reason why FPGA vendors tend to include a crap ton of pipeline registers in such blocks.

I am using BRAM that can be accessed from the AXI bus as well as through the programmable fabric (Xilinx Vivado). The minimum it supports is 32bit wide BRAM, and have to use BRAM generator

[NorthGuy]

I am using BRAM that can be accessed from the AXI bus as well as through the programmable fabric (Xilinx Vivado). The minimum it supports is 32bit wide BRAM, and have to use BRAM generator

If you use 7-series FPGA, their BRAM is dual port. Each port can have its own read/write width. Thus you can give one 32-bit port to AXI and use the other 4-bit port for yourself.