DSLogic

[jancumps]

This proposal for logic analyzer/oscilloscope is preparing a launch on KS:

http://www.kickstarter.com/projects/dreamsourcelab/1909457015?token=48da08f5

No affiliation.

[alm]

The LA hardware looks like a good deal for the $50-$90 they ask. 100 MS/s (in 16 channel mode), 4 MS memory depth, trigger in/out, decent multi-level triggering with counters (though no protocol triggering), both state and timing mode. The specs also hints at two sets of threshold voltages for 1.8 V to 5 V logic. Whether they will actually deliver the hardware (at least they show actual hardware that looks like finished boards) and whether their software will be stable and of good quality is a different matter. From the pics it looks like a lot of the UI was inspired by the Saleae software.

The oscilloscope feature seems to be completely vaporware (they state that they hope the community will develop the front-end, which is the hardest part). I don't see the appeal of the wireless sensor units, it looks like a fairly niche application to me. Are you really going to be sampling your temperature sensor with a logic analyzer?

[jancumps]

They mention protocol triggering in a video. I'm also not that interested in the scope part. It's the logic analyzer that seems to be decent.

[Marco]

Are they being disingenuous by saying "open source" a lot while not talking about the software or is it just an oversight?

[MacAttak]

Often, open-source projects that do crowdfunding campaigns will not release the source until they ship (or close to it). Sometimes the relevant source code and schematics (whichever is applicable) will be available from the start, but that is less common.

[Marco]

It's not so much the timing of release I'm concerned about, it's that they only say open source in relation to the hardware.

[Stonent]

"Arduion"

[Stonent]

[Rasz]

Open workbench logic sniffer with added
- Cypress FX2 for usable transfer BW instead of original pathetic serial port emulation
- ram chip

Looks nice.

[alm]

Open workbench logic sniffer with added
- Cypress FX2 for usable transfer BW instead of original pathetic serial port emulation
- ram chip

- (what looks like) nice and finished software with actual support for its advanced triggering features

[Rasz]

- (what looks like) nice and finished software with actual support for its advanced triggering features

I would rather see them work on Sigrok instead. Even if their software works, it will be abandoned after campaign ends :/

[jancumps]

... Even if their software works, it will be abandoned after campaign ends :/

Don't most kicstarters have the goal to start something that lasts longer than selling off the product they're launching?

[biot]

I would rather see them work on Sigrok instead. Even if their software works, it will be abandoned after campaign ends :/

It is, in fact, sigrok. The GUI and underlying library were forked off some time ago from PulseView and libsigrok, respectively.

We are currently working with the DreamSource Lab people to have them release their source sooner rather than later, as is of course required by the sigrok license (GPL). If everything works out, the changes they made can then be submitted back into sigrok, which means they will certainly be maintained.

[Marco]

This makes the proposition a lot more interesting ... anyone familiar with any of the names behind this? Trustworthy?

[jancumps]

I don't know the names.
I think that what they propose is do-able. No super exotic parts like a thermal imaging device involved.

[Kean]

I'm a backer of this, but only for the starter kit.  I don't think the wireless feature will be useful due to bandwidth.  I guess it could be useful if you need some galvanic isolation.

I really hope the software is up to scratch, and if as mentioned above it is enhancing sigrok (with appropriate contributions), then that will be very good.

Kean

[biot]

Just to follow up: the DreamSource Lab people have updated their kickstarter page to give credit to sigrok and the many other projects we depend on, and have released the source code. It's not in the form of a set of git patches -- more a dump -- but that works for now.

The  driver for their hardware is not included yet.

[nctnico]

The specs are a bit wild. High speed digital signals need lots of attention in the area of signal integrity. Despite the high sampling rate I wouldn't expect this board to be useful over several tens of MHz. A logic analyser needs proper probes just like an oscilloscope.

[free_electron]

That is my worry too. The front end consists of two stupid clamping diodes and a series resistance.

That doesn't cut it for me.
I'd like to see real programmable thresholds maybe in two banks of 8 bit each. And a better connector than the stupid 100 mil pinheader. Can we at least have a woven flatcable with proper termination  ?

[zapta]

Are they being disingenuous by saying "open source" a lot while not talking about the software or is it just an oversight?

"All of our design files(software/firmware source code, schematic diagrams, board designs, and bill of materials) will be open source."

[pinkysbrein]

Can we at least have a woven flatcable with proper termination  ?

Does the fpga have on die termination? How relevant is termimation though?  Unless you have an active probe or a dedicated test port won't you usually rely on a high impedance input?

[free_electron]

Very relevant ! If you screw up the edges of the signal you can kiss the timing corellation goodbye.

It's not hard to make a nice terminated testpoint for a logic analyser. Two resistors and a small cap is all that is needed. Agilent publishes the schematic of their breakout cables.
All you need is a small pod with a buffer chip driving the flatcable and a pigtail containing the rc network.

Heck , you could even make the analyser with the idc connector as used by the agilent 6000 and 7000 series MSO's (or the 54645d).

Those cables , i cluding pods and pigtails , can be had for 50$ on ebay.

I would redesign the analyser to fit a nice sturdy metal box with that idc connector, a few sma connectors for a clock input and a trigger output.

I knda like the design of this analyser because
- it has real sample memory
- it is fast
- it can do sequence triggering
- has good looking software that is not a kludge of 25 tools required to even view something

I don't like it because
- it is a bare, square , empty board not designed to fit anything
- the input circuits are junk
- it uses stupid 100 mil sideways pi headers (fro. What i can tell SMT nonetheless. A very bad idea as this is a connector that will be under substantial mechanical stress due to frquent plugging and unlkugging so the chances of ripping it off the board are much higher than with a thru-hole
- it has no box. I dont want bare boards dangling on a testbench causing shorts and other misery with the item under test. Test equipment must come in a case.

[Marco]

Very relevant ! If you screw up the edges of the signal you can kiss the timing corellation goodbye.

Yes ... but reading up on it, it's not really termination.

The logic analyzer inputs for those Agilent PODs seem to have around 10K input impedance (and 100 pF capacitance in the probe cable) forming a 10x divider with the RC networks in the probes or on the board. It makes sense, but needs a lot more circuitry than just termination.

[Jon86]

Very relevant ! If you screw up the edges of the signal you can kiss the timing corellation goodbye.

It's not hard to make a nice terminated testpoint for a logic analyser. Two resistors and a small cap is all that is needed. Agilent publishes the schematic of their breakout cables.
All you need is a small pod with a buffer chip driving the flatcable and a pigtail containing the rc network.

Heck , you could even make the analyser with the idc connector as used by the agilent 6000 and 7000 series MSO's (or the 54645d).

Those cables , i cluding pods and pigtails , can be had for 50$ on ebay.

I would redesign the analyser to fit a nice sturdy metal box with that idc connector, a few sma connectors for a clock input and a trigger output.

I knda like the design of this analyser because
- it has real sample memory
- it is fast
- it can do sequence triggering
- has good looking software that is not a kludge of 25 tools required to even view something

I don't like it because
- it is a bare, square , empty board not designed to fit anything
- the input circuits are junk
- it uses stupid 100 mil sideways pi headers (fro. What i can tell SMT nonetheless. A very bad idea as this is a connector that will be under substantial mechanical stress due to frquent plugging and unlkugging so the chances of ripping it off the board are much higher than with a thru-hole
- it has no box. I dont want bare boards dangling on a testbench causing shorts and other misery with the item under test. Test equipment must come in a case.

The best thing about this project is its simplicity. No stupid showy enclosure, no annoying proprietry connectors. Start adding all that stuff in and the cost is going to be through the roof.

[Marco]

How would you cheaply build a high speed logic analyzer input stage for a 10x probe any way?