The Rigol DS1052E

[pheller]

Single mode allows the scope for a single trigger to be activated. So it could be called "one-shot", in other words it waits for the trigger and then acquires data until it reached the end of the screen or the end of the memory. Now I haven't one by hand, but I think it should acquire one screenshot, since by setting the sampling rate (or the timebase, if the ratio between these two is automatically set by the scope) you can decide how much time you'd like to record.
It is used for seeing rare events, or events that are each different one from the others, even if they all could activate the trigger For example, if you want to see the response of a program on an MCU to the first time it receives a byte on the UART, you can set trigger mode on "single", falling edge trigger on the RX signal and a proper timebase, so that the screen contains the whole response of your interest. If on the UART there will be other data after the first byte, and if you were on "auto" or "normal" mode (instead of "single" you will see the series of the various responses together, so not letting you see how the first was.

Thanks for the response.  I had also thought it might capture to fill the memory (or enough memory to fill the screen, based on horizontal timebase), but I'm a newbie with a scope, so wasn't sure. 

I'll give it a go tomorrow to verify the operation.

Thanks!

--phil

[Fraser]

I have just completed a strip down of my DS1052E - Hardware Version 58. Purchased in September.

It was an investigation into an impact sensitivity problem that the scope had. It turned out to be loose screws and BNC nuts !

Whilst investigating the problem I had a good look around the motherboard and did not see any differences to the pre HW58 model so any that are present are minor. The CH1 & CH2 input circuits appear to be the same. They still have the varicap diode based bandwidth limiter and no effort has been made to deter a hardware modification. (not that such is now needed).

What may be interesting to some is the fact that the usual IC's have been anonymised by removal of their ID markings but my scope contains IC's that appear to have been sand blasted in a very professional manner. A neat little abraded square is present on the chips rather than the usual Dremmel grinder aftermath. Very neatly done and very effective as no remnants of the chip ID remain.

Build quality is still good, with good component placement and quality soldering but PCB 'hygiene' is poor as evidenced by finger prints and detritus on the top and bottom of the PCB (this scope is brand new). Not great but no big issue for me as the unit now works well.

UPDATE:

Pictures have been added.

I have just looked at the pictures of the earlier Rigol DS1052E SMPSU and compared them to mine. There is a difference. It would appear that the high voltage CCFL power supply has now been deleted. This would suggest that the newer DS1052E may have an LED backlight for the LCD panel. I have not, however, proven this by test.

[rf-loop]

What may be interesting to some is the fact that the usual IC's have been anonymised by removal of their ID markings but my scope contains IC's that appear to have been sand blasted in a very professional manner.

They use laser.

[saturation]

Kudos Aurora, to a great job.  More to follow as I 've time to digest details.

[EECrAZY]

From the pics, looks like later versions have a mechanical AC/DC coupling relay instead of a solid state one. Another difference I noticed, input FET transistor marking changed from “K51” to “6U” which is MMBFJ309LT1. Part number with k51 marking was unknown. Thank you Rigol for giving us another part number

I am curious if anyone figured out the part number for the buffer op amp right after VGA?
And what is that analog support circuitry is supposed to do? As far as I found out, there is a high speed comparator there, a couple analog multiplexors and a bunch of low speed P274 dual opamps if I am looking at the right part for IC with p274 marking.

I am trying to have a more in depth picture of what makes this beast tick and would appreciate any input

[tinhead]

funny, the input circuit is not much different than the one from Tekway DSO:

https://www.eevblog.com/forum/index.php?topic=1571.msg21235#msg21235

The small ADC driver chip is in a LLP-8 package seems to be really LMH6552 (maybe hard to see on my picture but it is marked 88AB / 6552)

[EECrAZY]

Yeah, looks like Tekway is a improved copy of Rigol with some changes on ADC/FPGA/LCD part.
Analog inputs are just routed differently and all that trigger support circuitry looks also very similar with the same parts...
I am still curious what is all that circuitry is supposed to do? Would not 1 comparator be enough? I noticed there is a LT1790 reference chip,  I thought it could be used for self calibration, but turns out like it feeds a REF pin of LTC2601 DAC. Rigol board does not have those parts.
There are a few analog multiplexers there with -1Db drop at 100Mhz, Could that be a bottleneck? Seems like the rest of the components would handle 200Mhz+ not a problem

[EECrAZY]

that's the self-calibration unit, it runs with 125Mhz.
 

Do you mean that it has a 125Meg oscillator on board which is used for the sole purpose of selfcalibration???

[tinhead]

that's the self-calibration unit, it runs with 125Mhz.
 

Do you mean that it has a 125Meg oscillator on board which is used for the sole purpose of selfcalibration???

i've answered here:
https://www.eevblog.com/forum/index.php?topic=1571.msg22123#msg22123

let's leave Rigol thread only Rigol related (even if probably Rigol is using the same self-calibration way but with different DAC)

[EECrAZY]

Ok, finally took my rigol apart, warranty sticker removes very easily using the same method people use on xbox.
Measured some signals, there is a small DAC chip with "D5G" marking. Looks like its constantly fed  by CPU/FPGA, so the output is steps of different height.
DAC output feeds two 4051 multiplexors, which are being  switched by 8khz counter.
I am wondering if they use this approach to generate offset voltages, trigger levels etc with only 1 DAC?

[dealexcel]

Ted come here again, if you guys are still interested in ds1052e scope, welcome to my site anytime

[Mechatrommer]

Ted come here again, if you guys are still interested in ds1052e scope, welcome to my site anytime

update your own thread!

[EECrAZY]

Turns out that I was right in my previous post, single DAC output is multiplexed and used to generate multiple voltages for A,B offset as well as trigger level.

Interesting thing is that it also generates a saw like voltage with 2seconds period! Any ideas what it can be used for? I was not able to trace where its output goes.

Another interesting thing is they always clock ADCs at 100MHz, even at the lowest sampling rate. So I guess FPGA just skips unwanted samples. Would be nice if it could go down to 20Mhz at lower sample frequencies, I am sure it would reduce the heat quite a bit

[EECrAZY]

Rigol’s 1Gs interleaved ADCs seem to be a problem and completely useless at higher frequencies

Upon further analysis of their schematic, it turns out that all ADCs are clocked directly from Cyclon III FPGA. Looking at the datasheet, Cyclon III PLL has 300ps of jitter on the output clock… that means sample uncertainty of 300ps! Using a standard equation we can determine that at 100Mhz input frequency, we have SNR of only 20db! Or effective resolution of 3.4 bits.

Note that unlike offset and gain errors, those 300ps are random and can not be corrected by any digital post filtering

Please correct me if I missed something. Any ideas from the experts?

[Fraser]

Hmmmm. 300ps jitter present at all times or maximum of 300ps jitter worst case scenario. There is a difference.

We already know that Rigol have employed some clever(?) tricks to provide a 1Gs/s DSO at a great price. Should we not be testing and reporting the real world performanace rather than using a chip manufacturers worst case scenario jitter figure ? Just a thought.

[EECrAZY]

yeah, 300ps is a 10^-12 probability (14 sigma) peak to peak jitter. So really it translate to 20ps rms jitter which would give us 44 db SNR or resolution of 7.3 effective bits.

I agree that this tool is worth the money, One thing I dont like, they pushed it to 1Gsa for marketing purpose because higher numbers bring customers. They know most of us cant really tests the performance up to the limits, especially considering a low end market.

I would really like to see some real life measurement at 100+ Mhz input and 1GSa. I bet you should be able to see some noise due to interleaving multiple ADCs

[tinhead]

correct me if i'm wrong, but isn't for interleaved ADCs the clock shit accuracy more important ? That's 50ps between rising edges of each clock period (which is probably measure period).

In a worst case we can still solder 10bit ADCs (AD9218, pin compatible to AD9288) and use only 8 MSB bits ^^

[EECrAZY]

correct me if i'm wrong, but isn't for interleaved ADCs the clock shit more important ? That's 50ps between rising edges of each clock period (which is probably measure period).

In a worst case we can still solder 10bit ADCs (AD9218, pin compatible to AD9288) and use only 8 MSB bits ^^

In ideal world you would have 10ADCs sampled at 10ns with 1ns phase shift. Lets say due to clock jitter this phase shift varies randomply from 0.9 to 1.1 ns. That creates an uncertainty window of when sample is digitized.

Using a 10 bit ADC makes no difference if effective number of bits is 7. You only need 7 bits to resolve your signal above the noise floor. 3 LSBs will be randomly floating (measuring random noise). In case of 8 bit ADC 1 bit will be measuring noise

50 ps phase shift error you mentioned is constant. Unlike random jitter, it can be eliminated by calibration.

[tinhead]

Exact, in the theory each ADC is sampled with 1ns phase shift with no jitter.
The sampled data is available always on rising edge (actually after aperture delay).

The 300ps PLL jitter is a full period jitter, but we still within one period so the "jitter" is only ±50ps due PLL shift inaccuracy.
After such full sample cycle of course there can be 300ps jitter to next rising edge but that's different story, there will be anyway
"a window" due 2000 waveforms/sec.

Not sure how Rigol is using the ADCs, but probably with data align enabled - each ADC in AD9288 shifted by 180°
and all AD9288 shifted by 2ns to each other.

btw, the 10bit ADC was a joke ^^, it will requiere clock with less jitter anyway.

[EECrAZY]

Well, yes and no. May be data within 1 period is indeed not affected by period jitter. But you still need to have evenly spaced samples.  Looking at 10ns of data is impractical in most cases, so you will see visual distortions and much more noise on FFT.

Actually, I dont believe AD9288 data align provides 180 degree phase shift. Its only for the output, data is still sampled independently on the rising edge of each clock. But output from channel B is 1/2 period delayed.

[tinhead]

Actually, I dont believe AD9288 data align provides 180 degree phase shift. Its only for the output, data is still sampled independently on the rising edge of each clock. But output from channel B is 1/2 period delayed.

well the clock need to be shifted by 180 degree for data align.
I did checked my Tekway, and it is not using this mode. Actually it is set to S1=1 and S2=0,
so sampled data and clock are both shifted by 180 degree.
As this is standard mode with two clocks Rigol will have probably same settings.

[Mechatrommer]

keep up the good work! i'm looking forward to see any new hack/improvement or detailed performance report coming in.

[EECrAZY]

I did checked my Tekway, and it is not using this mode. Actually it is set to S1=1 and S2=0,
so sampled data and clock are both shifted by 180 degree.
As this is standard mode with two clocks Rigol will have probably same settings.

No, just checked my Rigol and both S0 and S1 pins are tied to Vdd. It does use phase align, though it makes no difference  hence you still need 10 clocks shifted by 1ns

[flolic]

Maybe someone can unsolder the varicap and test with 2 x 2.2pF (1.1pF total) in series, i can't because i'm Tekway/Hantek "junkie" (flolic maybe you?)

You mean to solder 1.1pF instead of varicap? Yes, I can try that. But I removed that 160pF caps long time ago... 

[saturation]

There's an interesting review of the 1052E from a Chinese electronics blog by Dengbao Ming, who has excellent electronics info on his blog from a China perspective [ in Chinese], and Rigol in general.

Here he suggests the 1052E achieves price/performance by overclocking its ADC:

http://translate.googleusercontent.com/translate_c?hl=en&sl=zh-CN&u=http://tm.eefocus.com/stupid/blog/09-08/174557_df398.html&prev=/search%3Fq%3D3458a%2Breview%2Beefocus%26hl%3Den%26safe%3Doff%26client%3Dfirefox-a%26hs%3DPGy%26rls%3Dorg.mozilla:en-US:official%26prmd%3Div&rurl=translate.google.com&twu=1&usg=ALkJrhiSnedF1biRtFDQGEQxdg7c2i3VgQ


He suggests, in reading through his his commentary, Rigol copies Agilent products, while Tekway copies Tektronixs.

In this editorial, he discusses a Japanese article comparing 100MHz scopes, and the Rigol does quite well:

http://translate.googleusercontent.com/translate_c?hl=en&sl=zh-CN&u=http://tm.eefocus.com/stupid/blog/09-12/182020_8ab4d.html&prev=/search%3Fq%3D3458a%2Breview%2Beefocus%26hl%3Den%26safe%3Doff%26client%3Dfirefox-a%26hs%3DPGy%26rls%3Dorg.mozilla:en-US:official%26prmd%3Div&rurl=translate.google.com&twu=1&usg=ALkJrhhFUMkVbRLCNl6yKQ_PtP6JsCv26Q

He also link eevblog articles on the Rigol from 2009.