Rule #1 of MOSFETs is that you never leave the gate floating. Because they are essentially infinite impedance at DC, there is no bias current to pull it into a well defined state. Both stray electric fields and the parasitic capacitance to the gate and source can easily push it around. The most common result is oscillation: if the gate picks up a bit of charge the channel starts to conduct. The current draw pulls the drain voltage down towards the source, and the drain-gate (miller) capacitance drags the gate down with it. This causes the transistor to shut off, and the drain voltage rise. Again, the capacitive coupling causes the gate to try to follow the increasing voltage of the drain and the FET turns on again.
The dynamics of what actually happens depend on the series resistance on the supply, the parasitic capacitance, and the circuit environment in which it is connected. MOSFETs in integrated circuits usually have protection diodes connected to the supply rails. The reverse leakage current of these diodes also affects the biasing. Logic inputs have a complimentary pair NMOS and PMOS with their gates tied together. Here, the common result is for the gate to float to halfway between the supply voltages so that both transistors are turned half-on, causing a large class-A current to flow, possibly overheating the device. In any case, free floating mosfet gates are extremely susceptible to pickup of stray fields, so if nothing else you are likely to see oscillation at 50/60 Hz.