You can't just whack in an FPGA and get this kind of update rate.
the biggest gap in all china DSO design is the splitted functionality - on part managed by FPGA, one by µC.
To get more wfrm/s they have to move as much as possible from µC to FPGA.
Currently Rigol E/D series/UNI-T/Atten are using DSP, which is resulting in max 800wfrm/s where Hantek/Tekway is using Samsung SoC
giving them 2.5k wfrm/s. No idea what Rigol CA series is using, but seems to be still a bit better DSP giving them 2k wfrm/s.
You can't just update the µC to higehr model, sure an ARM11 with 1GHz will maybe give you 5k wfrm/s, but this is still factor 10
slower than an "proper design" - far away from what an ASIC or better FPGA can do.
Rigol seems to have enough knownledge to do it better (DS6000) but this is definitely not an entry model class of DSOs anylonger.
The other (chinese) competitiors have to learn first how to move as much as possible of the core functionality into FPGA.
The Cyclone III is definitely to small, they will have to switch over to much bigger Cyclone IV
or Stratix III - this costs time, and time is money.
For LeCroy and Tektronix this might bea bit easier, depends of course on what they already have in their lab.
On the other side, even if it will be still far away from what Agilents ASIC can do for same money
and Agilent can still update 2000x series with the crippled 3000x ASIC, to get let say 200k wfrm/s and 1Mpts.
The "biggest gap" of Agilents 2000x is the 100kpts memory, but if the ASIC is the same in both models a memory update could
be still possible - if not 2000XA will be released.