Sorry but that "micro circuit" is not what was used in the Apollo AGC.
First two versions of AGC existed the block I and the block II. The block II was a lot more that just made with different chips, they made some changes to the hardware as they found out things they needed/missed in the early specs. The block I did fly, just not on any maned missions.
The first problem with that package that was sent in was both the block I and block II machines were made with 3 input NOR gates, not 2 input gates. We look at it now and think that was stupid, but in fact it was a great idea for the time. One part. Fairchild could ramp up production, tweak the process and get the MTBF way down. Check some of the documents on the net, there are graphs and charts of failure rates of the 3 input NOR gates.
The block I chips were also a single gate per package, thus it took 4100 chips in a TO style case.
The block II on the other hand went to flat pack dual 3 input NOR gate, and took 2800 of those.
A few other things that need to be corrected, it was not 16bit machine, it was 15bit, but memory had a 16th parity bit.
Memory layout was strange because the code and variable store kept growing and you only had so many bits in the the instruction for addresses. They had to do banking and add registers that controlled banks. Even that wasn't enough and they added a bit in one output channel for a "super bank".
The other odd thing about the machine was it's math, it was one's compliment rather than two's. This made for a few odd things like a positive and negative zero. Fine for most stuff but not when the hardware bumps up or down counter in memory each time a gyro sends a pulse. It think I saw some paper from one of designers that looking back the ones's compliment was a poor design choice.