With hindsight, I can see two ways of avoiding the problem in future.
1/ do your polygon pour at 8 thou clearance and check the DRC. If OK, re-pour at 6thou and submit.
2/ add a deliberate track under the polygon pour to ensure connectivity.
It is amusing (in a way) to get this sort of result from the ultra precise Altium package.
I have been known to have similar issues with polygon pours when panelising many identical boards onto one large panel for another PCB service.
My problem was the copies were pasted without netlist connectivity (avoids the ratsnet appearing between boards).
The problem was allowing a polygon re-pour after the no netlist paste.
Result - instant isolation of all ground pins from the polygon pour.
Arrgggghhhh - wasn't funny at the time, but once the pain wore off
BTW despite the issues, the boards look great, must give them a go myself.
Reasonable turnaround?