Great job on the teardown Dave! I liked how you overlaid the block diagram on the circuit board photo.
A few comments:
[7:00] The unloaded IC, U15, to the left of the Spartan 6 FPGA is probably a for second bank of DDR memory that isn't shared with the host processor. The additional memory is to provide data buffering for the DSP operations in the Spartan 6. This would enable a number of high performance features: real-time spectrum analyzer operation, digital modulation signal analysis, etc.
[23:17] The input switch U1 switches the RF input to the 50 ohm dummy load when there is an overpower condition. The unloaded diodes D31-D34 could be the detector or they could be limiters with an adjustable threshold. Perhaps these diodes were not loaded because they degraded input IP3 and/or caused a rolloff in the frequency response.
The following switch U2 has a trace on pin 1. It is likely for a calibration signal as G0ZHU mentioned. By providing a reference signal, the signal path amplitude drift vs temperature can be compensated to some degree.
The preamp used non-reflective SPDT switches to increase isolation and terminate any stray leakage into the thru path, which feeds back into the input of the preamp, causing oscillation.
[33:07] Your block diagram and photos provided enough information to deduce the frequency plan without doing any measurements.
[44:35] The ADC uses bandpass sampling to sample the IF. The Nyquist criterion requires that the signal bandwidth has to be less than 20 MHz. It doesn't mean the IF frequency has to be less than 20 MHz. With a bandpass filter around the IF signal, aliasing can be used to downconvert the signal in the digital domain.
70 MHz is the 3rd IF. Since the ADC samples at 40MSPS, 70 MHz will alias to 10 MHz, which in in the center of the first Nyquist zone.
810 MHz is the 2nd IF as you already discovered. This allows determining the 2nd and 3rd LO frequencies:
3rd LO = 880 MHz (810 MHz + 70 MHz)
2nd LO = 3520 MHz (880 MHz x 4)
The 1st IF is thus 4330 MHz. (810 + 3520 MHz)
1st LO range at mixer port: 4330 MHz to 6430 MHz (to 7530 MHz for 3.2 GHz model)
The 2.1 GHz and 3.2 GHz model share the same RF design as one would not use such a high 1st IF frequency and use a frequency doubler in the 1st LO path if the design were optimized only for 2.1 GHz.
[15:47] The TG offset synthesizer IC is a HMC835 (33-4100 MHz) according to the part markings, not a HMC832. It is set to 4.33 GHz, the same frequency as the 1st IF.