Level converter (ST2378E) why this pin location?

[josecanuc]

I was browsing some datasheets for level converters and came across this ST2378E https://www.st.com/resource/en/datasheet/st2378e.pdf which is described as an 8-bit bi-directional level converter.

Is there any particular reason why the high and low side data lines are on alternating sides of the TSSOP package? I/O_VL1 is directly opposite I/O_VCC1, which makes sense, and the pattern continues all the way down the chip, but the high and low voltages alternate sides.

To me, this only looks like it would complicate the PCB routing, but I've not done much of that, so I may be missing something.

[DTJ]

I have no idea why this is so but I often come across pin layouts on ICs that seem to be selected for maximum frustration.

Earlier this week I looked at a temp sensor IC. It had 3 x Vss pads down one side, 3 x Vdd pads on the other and 4 data I/O pads down the centre making it an absolute bitch to route.

[Psi]

Sometimes chips are first designed for a specific product/use but continue to be produced as a general chip.
They retain some weird design properties.

[pigrew]

I speculate that it simplifies the packaging of their IC or maybe die routing.

I postulate that they use the same interposer & leadframes for multiple products, so there would be a fixed mapping between the C4 bump and the package pin. They would have designed their die's C4 pad layout for one or the other, and they chose BGA, as everything is nicely laid out (columns 1 & 2 are VL, columns 3 & 4 are VCC). For TSSOP they'd mount the die upside down under the lead frame.

SOIC lead frames are single-layer routed, so they can't have crossing tracks. However the BGA package probably has two layers with vias so they have much more routing freedom.

Maybe their ESD protection cell is much larger for the VCC side (if they use double-diodes on the VL side connected to the VCC rail), so in die layout they alternated the large ESD cells in order to make die routing easy? On the VCC side, they'd need a RC clamp cell. Yes, they should be able to get away with a single RC clamp cell for the entire bus, but they seem to have stupidly high ESD ratings on this part, so they may have had to do something out-of-the-ordinary for it.

It does greatly complicate PCB routing, but they likely expect you just route the tracks between the leads on the opposite sides.

The only way to know is to take apart the package and see how it's routed (or to ask the designers).

[wraper]

Most likely because designers had a choice of making it like this or increase die area. Thus making IC more expensive to produce.

[T3sl4co1l]

Compare originals like 74374 to their improved versions like 74LS574.  Still not terribly hard to use (snake traces between pins) but a bit odd.

Some CD4000 ICs had some really weird pinouts.  I forget if any (or which ones) broke from the VDD/VSS-in-corners custom, but I think that happened?

Another oddity: sometimes a device in one packaging (DIP, SOIC?) has different pinout from another (TSSOP, no-lead?).  This often happens when the rectangular die doesn't fit in the smaller package with the same orientation, but does when turned; so if you look closely at the pinout, you'll realize it's the same sequence, but rotated 90°, so what used to be pin 1 is now in the middle of one row.

Tim