The O.P specifically asked "Does this circuit looks legit"?
Its the absence of a base resistor for the PNP transistor that should clue you in that the O.P's found circuit may have problems. Combine that with the 100R load on the
CD4011B final output, and looking at datasheet figs. 5 & 6 'Output High (source) characteristics', its obvious that if you want the transistor off when the CD4011 output is high, it must source well under 2mA. That means the Vf of VL1 must be at least 11.2V (12V supply - (0.6V Vbe + 0.2V drop across R7)). VL1 must therefore be a compound LED consisting of a series string of dies, which is typically only done where high intensity is required, and running it at under 2mA is unlikely to produce sufficient illumination.
Also it is immediately obvious that the output must pulse if it indicates anything, as the NAND gate after the flipflop has one input fed from phase L1, forcing the output high for a minimum of 50% of the period.
A circuit can be bad even if one working unit has been built. e.g. if it takes no account of component tolerances so will only work if you are lucky or if you select for particular tolerance extremes.
If you can at any time prove me wrong, I'll thank you for doing so.