how does blackdog's PSU work?

[exe]

Hi!

I'm trying to design my own PSU. I took @blackdog's power supply as a reference (schematic attached). But the more I study it, the less I understand how it works.

1) The output voltage is defined by current flowing through resistor P2  (20k multi-turn pot). But why voltage drop on P2 should be constant? I don't see a current source to ensure this. I only see a voltage source which is +5V above the positive output.

2) what is return path for current flowing through P2?

[T3sl4co1l]

1. Consider what the op-amp inputs see, as output voltage varies.

2. Through the output node.  Note that all the little bias currents from the reference section act to pull the output down.

The circuit in general:

Oh geez, those aren't fucking JFETs.  Who drew this...

Anyway: this is the only amateur linear power supply design I've seen that is actually reliable, and working, as shown.  (Compare to the 30V 3A mega-thread, or whatever it was, which is a living train wreck...)

It makes some strange decisions, like using an active rectifier (doesn't really matter; easily substituted with a cheaper, traditional, FWB diode), and schottky diodes alongside shitty old 1N4001s, which can be more coherent.

Interestingly, the V/I error amps have low integrator windup.  I can't decide if this was by cosmic coincidence, or full top-down intent.  It's quite possible that the decision to fix the reference above the output was a direct consequence of this step -- a lot of trouble to go to, but as long as you're going to go that extra kilometer, you get something nicely behaved indeed.

I think the only things I really object to are:
- The fuse is silly.  If fault protection is desired, a current limiting stage can be added, at the input or output.
- The "dropout protection" circuit doesn't make sense either; if you're going to specify ~200W worst case dissipation, don't hack it, just put in enough transistors and heatsink to handle it.
- A preload (besides the reference bias) on the output would help by biasing the output stage into conduction, improving transient response (the problem is all the nonlinear junctions -- the output transistors and LEDs, aren't fully conducting at the no-load condition).
- Get rid of the output capacitors, or use minimal amounts.  Also, why bother buying a low-ESR cap, just to put a resistor in series with it?  Is compensation really that critical that it needs a 10% stable ESR?

Overall, small complaints, and simple tweaks.  This is a good design.

Tim

[exe]

Thanks for answering. I'm still digesting the circuit. I tried to "think as an opamp", still don't get one thing:

1) If output voltage goes up, the voltage on P2 also goes up?? Why doesn't swing up to maximum or oscillate? (Unless C24 smooths voltage good-enough so the circuit does not oscillate).

2) Can I drive current-setting and voltage-setting resistors with a DAC?

3) Is it really necessary to have TL317 and LM329 in front of LT1021? Looks a bit over-engineered to me. Can I just use a 6.2V zener and 2n3904  emitter follower as a pre-regulator?

[blackdog]

Hi,

Que? => Oh geez, those aren't fucking JFETs.  Who drew this...
I have drawn this schematic and extensively tested! :-)

About the active rectifier, which is to limit the power loss, that should be clear...
If you want to throw away a extra 10-Watts, be my guest, no problemo to use diodes.

The pre regulator works, just adjust it for your transformer, and why did i drop this part of the schematic?, because 2 transformers (2x9V) and some relay, works without winding noise of the transformer.

I do not understand why over and over again people whine over the reference section, it is to much, overdesigned etc etc.
The Architect specifications were LOW NOISE! High stability, at full load, and i mean < 5uV rms, and Yes! i mean uV and not mV.
The reference section is not overdesigned, but well designed!
If you want to have an average power supply, build somting else 

The currentsource make the power supply extreemly well regulated.

Why Low ESR components on the output, because these are almost always, also good quality components.

The fuse is only for calamities, probably never blown up, if you want to kick it out, your problem 
 
Get rid of the output capacitors, or use minimal amounts NO, NO, NO! 
These capacitors with the series resistors and the loop time constant determine the dynamic behavior of this power supply.

 
Look at this picture...


A 9.5-Ampere Puls generated bij my Dynamic Load, the opamp at that moment was the NE5532A and the output network used is in the picture.
The ringing you see is NOT! the power supply, but my Dynamic Load connected to the powersupply under test via twisted 0.5M cables and a high quality 6.8uF capacitor over the Dummy Load connection.
If i remove the 6.8uF capacitor, then there is no ringing, just a short puls of about 5mV piek for every 5A change and totale gone in about 25uSec.
The residu of the twisted cable induction and the 6.8uF capacitor create's the ringing, this is a difficult test for power supplies and i use it a lot.

Kind regards
Bram

[T3sl4co1l]

I have drawn this schematic and extensively tested! :-)

Ok but why JFET symbols?  Those are unambiguously JFET symbols, and the devices are unambiguously not JFETs, but MOSFETs.  Was this drawn in a package that doesn't have a MOSFET symbol and doesn't allow symbol creation?  (If so, please let me know so I can advise everyone to avoid it like the plague...)

(Similarly for the schottky diodes, but that's a lesser sin.)

About the active rectifier, which is to limit the power loss, that should be clear...
If you want to throw away a extra 10-Watts, be my guest, no problemo to use diodes.

Doesn't bother me, on top of a 10W, 100W or more loss in the pass reg.  If you needed efficiency, the whole thing would be a switcher (which, yes, can be as low noise, but -- it also takes more work to get there).

If you had a...

The pre regulator works, just adjust it for your transformer, and why did i drop this part of the schematic?, because 2 transformers (2x9V) and some relay, works without winding noise of the transformer.

Ah, so there was a pre-reg or tap switcher or the like, that would improve efficiency notably, allowing one to save on heatsink area.

The question is then: what thermal protection is there?  Easily enough added (or omitted(!)), of course.

I do not understand why over and over again people whine over the reference section, it is to much, overdesigned etc etc.
The Architect specifications were LOW NOISE! High stability, at full load, and i mean < 5uV rms, and Yes! i mean uV and not mV.
The reference section is not overdesigned, but well designed!

Well, let's see.   LT1021-5 claims about 60 dB PSRR at 15V and 10kHz; at 8V, it's down about 5dB, so let's say 55dB.  That means its supply can be about 35000 nV/rtHz, to only increase the output noise spectrum by 3dB.

That's pretty fuckin' noisy!

On analysis, this would seem to be overkill.

Unless you have measurements showing it both ways (e.g., LM317 alone, with resistor divider; versus with LM329).

I didn't notice this point originally, but it's a fair point, and I see no data or argument defeating it.

The LT1021 doesn't even seem to be very good; an array of TL431s can do better, and might be cheaper.  REF50xx do better, dunno if cheaper.  I don't regularly shop for references.

The currentsource make the power supply extreemly well regulated.

??

Get rid of the output capacitors, or use minimal amounts NO, NO, NO! 
These capacitors with the series resistors and the loop time constant determine the dynamic behavior of this power supply.

 
Look at this picture...

I'm looking.  It looks pretty damning...

A 9.5-Ampere Puls generated bij my Dynamic Load, the opamp at that moment was the NE5532A and the output network used is in the picture.
The ringing you see is NOT! the power supply, but my Dynamic Load connected to the powersupply under test via twisted 0.5M cables and a high quality 6.8uF capacitor over the Dummy Load connection.
If i remove the 6.8uF capacitor, then there is no ringing, just a short puls of about 5mV piek for every 5A change and totale gone in about 25uSec.
The residu of the twisted cable induction and the 6.8uF capacitor create's the ringing, this is a difficult test for power supplies and i use it a lot.

...Oh.

So, wait.  You performed a test, on a power supply, that does not measure the power supply's characteristic, but some external network instead?

Can you please explain that rationale to me?  Because that can't possibly be right.

The network should be around 0.3uH + 6.8uF --> 110kHz oscillation.  I don't know why the measured pseudofrequency seems to be ~half that.  It probably has to do with why the damping is modest, too (maybe the load is not simply an on/off switch and resistor, but has 10uF + 0.05 ohm in parallel with it, perhaps).

The voltage ripple should be measured at the power supply output terminals, which is the only possible point the power supply can control, after all (at least without remote sense terminals included).  The load step should be nothing more than a resistor and switch, with minimal damping.  Its rise time will be limited by cable inductance to about 0.6us, which is fine.

...Double-wait.  Why is the test at 9.5A when the supply is rated for 5A!?  Why is it not dropping out during the pulse?

This data is inconsistent and thus wholly unusable.  Who knows what it was measured on!  Are you a liar?

You realize you aren't making much of a case for this, right?

I guess I might as well retract my claim that it's good.  It's still better than others as I said before, but this disregard for data and measurement bothers me much more than the otherwise minor inconsistencies in the design. 

Tim

[T3sl4co1l]

Thanks for answering. I'm still digesting the circuit. I tried to "think as an opamp", still don't get one thing:

1) If output voltage goes up, the voltage on P2 also goes up?? Why doesn't swing up to maximum or oscillate? (Unless C24 smooths voltage good-enough so the circuit does not oscillate).

Well yeah okay, it goes up...

But the immediate words that should follow that are:
"How much?"

If P2 has, say, 5V on it, then the other input should be at 5V (which is also what the output will be at).  What does this tell you about the output voltage?  What does this tell you about the value of P2, with respect to R32?

What if P2 has 10V on it, what must the voltages (and P2 resistance) be?

Can we write a relationship (an equation) describing this?

2) Can I drive current-setting and voltage-setting resistors with a DAC?

Yes, but the DAC better have a wide voltage range!

3) Is it really necessary to have TL317 and LM329 in front of LT1021? Looks a bit over-engineered to me. Can I just use a 6.2V zener and 2n3904  emitter follower as a pre-regulator?

Unless the author can prove otherwise, I see absolutely, positively no degradation from simply using the '317 as intended, with a resistor divider.

Tim

[Cerebus]

3) Is it really necessary to have TL317 and LM329 in front of LT1021? Looks a bit over-engineered to me. Can I just use a 6.2V zener and 2n3904  emitter follower as a pre-regulator?

Unless the author can prove otherwise, I see absolutely, positively no degradation from simply using the '317 as intended, with a resistor divider.

Tim

Or simply use the LM329 (which is a pretty quiet reference, just as quiet as the LT1021 - 7 uV rms 10Hz-10kHz versus 2.2 uV rms 10Hz-1kHz i.e. essentially the same)  in the usual bootstrapped current source/reference amplifier, all fed by an LM317/whatever, as your core reference and derive all your rails from that - sprinkle with op amps and emitter followers to taste.

Then junk the £12.28 active rectifier setup for a £0.25 diode bridge and use the money you saved to upgrade your LM329 to an LM399, which will drop-in nicely with no re-design and lower your core reference tempco to 0.3ppm/C. 

[blackdog]

Hi,

I will try to explane some things, but bear with me, i am a dyslect and English is not my nativ langguage.
And of course... I am from Amsterdam in the Netherlands, that means that I am direct and do not lie , and no bullshit.

And again, the reference section...
The powerline at my lab is noisy and has a relativ high Ri.
Its a powerfull noise generator 

There are several tricks to keep the line noise out of the LT1021 and the LM334.
First the extra resistors R3 and R5 in combination with C3 and C4 yes low ESR types.
I lifted the TL317 regulator with D6, so the noise of the TL317 would not be amplified 6 or 7 times.
R23 and C20 makes another low pass filter, this has a double function, C19 en C20 makes a time constand, so there are no power on abberations.
The output of the TL317 is also used for the opamps.
The negative power supply for the opamps is just a simple zener regulator, and again C8 makes and R9 makes a slow power on.

Replacements for the LT1021-5V, but why... eat one big Mac less and you can affort a LT1021-5V...
Ore use one of these: AD587, MAX6350, MAX6126, LTC6655, LT1027 and if you have money to spend, buy a VRE3050 *grin*

Tim
I have explained before, that when I draw this schematic, I could not find the MOSfet in the library of my drawing package.

Power dissipation
There are several ways to limit the power loss, the dissipation limiter shown here is one of them.
But this needs some attention, for the transformer used.
The performance is good enough, but not as high as a switcher.
When using say a buck regulator (how often did I have to hear that ...) the efficiency is better.
Designing a extremely low noise 200-Watt pre-regulator is difficult.
After a number of measurements (test circuits) I decided not to use it. (Most switchers are like a Pulsar sweeping there powerful beam of noise, over sensetive electronics)
A transformer with multiple taps, or as I already mentioned, two transformers of 2x9V works well enough for me and saves enough energy.

Thermal protection
This is not the latest schematic, thre are some sensors on the power section and the transformer.

Current source
Sorry, i'am talking about the current source that is not in this schematic 
There is a current source (about 50mA) at the collector of Q2 or Q4, it alway puls this current out of the power stage.
This makes the dynamic behavior better and also ensures that the output voltage decreases rapidly when it is turned down at low load.

Power section
This is the best I could make, I also tested with smaller power transistors, this was a version with 4 compound stages.
I did blow up this version during testing and was worse in terms of Ri than the 2SA1943 / 2SC2911 transistors.
Why these transistors, this is to keep the delay of this stage as low as possible, so it would not at to much to the phase delay to the opamps.

Dynamic performance
Tim explane, why i may not show a picture of the performance, at a peak current of 9.5-Ampere?
And do you realy think i'am that stupid, that i measure the performance of this power supply at the dummy load input?
This is one of my tests of the power supply, how it would reacts in a practical situation.

And of course I also test in a different way, with my Jim Williams Dummy Load, which has a very high bandwidth and is then connected to the power supply to be tested without cables.
Search fore AN104 on the LT website, i use te MOSFet version.

For real!!!
...Double-wait.  Why is the test at 9.5A when the supply is rated for 5A!?  Why is it not dropping out during the pulse?
Of course i am a liar!
Why is er no dropping of the line in the middle of the picture at 9,5-Ampere...
Because the performance of this power supply is that good !!! 


There are many measurements and information about this power supply on this page, use google translate is you cant read Dutch.
https://www.circuitsonline.net/forum/view/110029

Kind regards
Bram

[mikerj]

For real!!!
...Double-wait.  Why is the test at 9.5A when the supply is rated for 5A!?  Why is it not dropping out during the pulse?
Of course i am a liar!
Why is er no dropping of the line in the middle of the picture at 9,5-Ampere...
Because the performance of this power supply is that good !!! 

A PSU with adjustable current limiting between 0-5 Amps should always drop out with a 9.5A load unless the current limiting isn't working?

[blackdog]

Hi mikerj,


A PSU with adjustable current limiting between 0-5 Amps should always drop out with a 9.5A load unless the current limiting isn't working?

Yes an no,  a part of the ennergy is comming from the output capacitors, and this picture is from one of my design stages.
And if i want to test at a 9,5-Ampere level or even 15-Amp to see how the output capacitors are behaving during dynamic testing, i will do that. 

Kind regards,
Bram

[Cliff Matthews]

..There are many measurements and information about this power supply on this page, use google translate is you cant read Dutch.
https://www.circuitsonline.net/forum/view/110029

Kind regards
Bram

Thanks Bram! I hope you don't mind it all complied into an English PDF?

I did a Google translate on the whole thread and pasted it to a 118meg PDF:
https://drive.google.com/open?id=1cEGFsj6kk3hI8KUnBXqF0GFBy2YFkUCL

There were 35 linked images that were too small to be usable, they are here:
https://drive.google.com/open?id=1iKNivHfgNfMc6xBsww707_LqQOR2TIin

[T3sl4co1l]

Yes an no,  a part of the ennergy is comming from the output capacitors, and this picture is from one of my design stages.
And if i want to test at a 9,5-Ampere level or even 15-Amp to see how the output capacitors are behaving during dynamic testing, i will do that. 

Kind regards,
Bram

A part, yes.

As you should always ask: "How much?"

We can use the capacitor equation to find out.

C is about 200uF, and pulse duration is 200us.  Therefore:

I = C * dV/dt
(9.5A) = (200uF) * dV / (200us)
9.5V = dV

The waveform shows less than 10mV of dV (100mV if it was 10x probe, I have no idea if that was accounted for or not), so this cannot be.

Indeed, since the measured dV is nearly zero, we can say with quite good certainty that nearly zero energy is exchanged with the capacitors!  Such is the begrudging truth about capacitors -- we almost always use them for dynamical stability, not for energy storage.  Energy storage is only relevant when the change in voltage is large.

Dynamic performance
Tim explane, why i may not show a picture of the performance, at a peak current of 9.5-Ampere?
And do you realy think i'am that stupid, that i measure the performance of this power supply at the dummy load input?
This is one of my tests of the power supply, how it would reacts in a practical situation.

Please correct me if I am wrong.  It doesn't seem to be a translation error; you specified a cable length and distant load capacitance, introducing dynamics other than the supply itself.

Tim

[blackdog]

Hi Tim,

1e
Can you explain to us, why you have such a negetive attitude?

2e
And again you give the impression that I am a liar, 10mV/Div you know for sure that you're not lying ...

3e
And of course I can not do a practical test, because according to your standards, you do not test a power supply in this way.

4e
So ... if you do not show better behavior, I will not give you any answer anymore.

Kind regards,
Bram

[Kleinstein]

The load test at 9 A is rather short - it's only 200 µs.  The current limiting needs some time to respond and in this example it looks like the 200 µs are shorter than the response time of the current regulation.

It depends on the application how much delay is good. In some cases a faster reaction might be required, but in many cases a slightly delayed response of the current limit is actually a good thing as the main application is as a voltage source.

The LT1021 might be a bit of an overkill for a power-supply, especially if a NE5532 OP is used.  For most cases I would consider something like 2xTL431 or an LM329 sufficient.

It is possible to set the voltage via an DAC. In this case P2 is replaced by a fixed resistor and the reference voltage is supplied by the DAC. This way of adjustment also has an advantage for the control loop. It makes the control loop independent of the set voltage and thus gives very similar dynamic response at all voltages. In the current version with P2 to set the voltage, the response can be a bit faster at low voltages and slower at high voltage. This mainly effects the low kHz frequency range and might effect the performance for the case of a very large load capacitance. At a very low voltage setting there might be a slight chance to have instability with a lot of low ESR capacitance  (e.g. something like 10000 µF of tantalum caps). In the extreme cases with the very fast loop also parasitic inductance of the layout and shunt can have an effect (both positive (especially for current control) and negative).

The case of large, low ESR capacitance is kind of the worst case for a voltage regulator and some ringing is normal in that case. One can not expect to reach no ringing in that case - already having it not oscillating with any passive (that is RCL type) load is good. A response with little ringing is only feasible and required for a much more limited load range. One should do tests for both cases: a difficult load (where quite some ringing is acceptable) and the more easy ones that should not show much ringing.

[Cerebus]

Hi Tim,

1e
Can you explain to us, why you have such a negetive attitude?

He doesn't, you just seem to react badly to any kind of criticism. Much of what Tim has had to say about the design is positive, but you choose to ignore that and over-react to the questions and criticisms. Vis:

Anyway: this is the only amateur linear power supply design I've seen that is actually reliable, and working, as shown.
...
Overall, small complaints, and simple tweaks.  This is a good design.

My experience of him tells me that Tim is both knowledgable and experienced, and generally quick to help. You can do one of two things, you can take advantage of Tim's interest and possibly improve the design or you can take offence, the choice is yours.

[blackdog]

Hi,

Here are some pictures of a test with the Jim Williams dynamic Load.
The current in this measurement is from 0,5A to 2A.
Opamp is the NE5532A.
Sensitivity of the scoop is 2mV/Div, no and I am not lying now 

This is the current puls, and yes, it is clean. 0.5 to 2-Ampere.


This is the respons on the power supply connector, about +-3mV abberation.


One of the the test setups.


This is a picture how i make a coax connection to the scoop or measuring amplifier, is has a angel of 90 degrees,
The BNC connector has an angle of 90 degrees to keep the coupling with the output wiring as small as possible.



Kind regards,
Bram

[blackdog]

Hi Cerebus,

OK This...
My experience of him tells me that Tim is both knowledgable and experienced, and generally quick to help.
You can do one of two things, you can take advantage of Tim's interest and possibly improve the design or you can take offence, the choice is yours.

So Tim is "mister know it all" (your opinion  ) and who am i, to reply on thing he says...
Uhm... Ooo Wait, I have designed this power supply and measured it extensively for my applications.

but you choose to ignore that and over-react to the questions and criticisms
Of course, I have not read that, and do you have a crystal ball?

The points that Tim touches I have a different opinion, and yes Tim, like me, is entitled to his opinion.
And yes, I think that Tim does have good knowledge of electronics, but I am not crazy either.

But, let's talk about power supply's designs and their set-up and applications 

Kind regards,
Bram

[Cliff Matthews]

Know-it-all's inject their image even when not wanted. I could make money just copy-pasting an encyclopedia out of Tim's contributions everywhere. I'm stupefied he never gets enough thanks. And.. if he's ever wrong, he's the first to facepalm himself.

Now back to your wonderful design good sir.. 

[steverino]

I have the greatest respect for Tim's knowledge and helpfulness.  I always thought he should be donated a "dumpster" scope for his prodigious contributions to this site (I think Tim is actually part electron  ).  Things seem to have gone off the rails when the strong word "liar" was used, which, understandably, Bram  (blackdog) became defensive.  (look at the trouble you created, exe  )  Hopefully, the discussion will continue without the heat.

[Cerebus]

Hi Cerebus,

OK This...
My experience of him tells me that Tim is both knowledgable and experienced, and generally quick to help.
You can do one of two things, you can take advantage of Tim's interest and possibly improve the design or you can take offence, the choice is yours.

So Tim is "mister know it all" (your opinion  ) and who am i, to reply on thing he says...
Uhm... Ooo Wait, I have designed this power supply and measured it extensively for my applications.

but you choose to ignore that and over-react to the questions and criticisms
Of course, I have not read that, and do you have a crystal ball?

The points that Tim touches I have a different opinion, and yes Tim, like me, is entitled to his opinion.

If you wanted to prove that you react badly to even the most lightly implied criticism then you have succeeded.

And yes, I think that Tim does have good knowledge of electronics, but I am not crazy either.

Again, nobody said that you were crazy. You just choose to be prickly and take offence at things that aren't said or implied.

I also think I catch a whiff of Dunning–Kruger effect here. You've clearly learned a bit, but you act as if you've learned it all, because you act as if you're too good to listen to anyone else.

So Tim is "mister know it all" (your opinion  ) and who am i, to reply on thing he says...
Ooo Wait, I have designed this power supply and measured it extensively for my applications.

You've designed and tested one power supply and you imply that is the ultimate in qualifications. That is being a "know it all" on scant evidence.

[T3sl4co1l]

Now that's much more reasonable, 1.5A step and a simple blip.

I don't get why it looks so ragged, if that's a noise thing or a trigger thing or what.  Or why the trigger is off at 239ms, maybe that has something to do with it?  Dunno.

But this doesn't resolve the inconsistency of the earlier screenshot.  If I had never seen that at all, I'd have no reason to doubt this!  But with?  I don't know.

The load test at 9 A is rather short - it's only 200 µs.  The current limiting needs some time to respond and in this example it looks like the 200 µs are shorter than the response time of the current regulation.

Shouldn't be a problem here -- offhand, if the current error amp has to slew 5V (it should really only be about 2V), it can do that, in and of itself, in less than a microsecond; and with about 100pF effective integration capacitance and a few kohms connected thereto, it'll only take about a microsecond.

So I'm still perplexed how the circuit (if it was, in fact, built and measured as shown) could do that.

The points that Tim touches I have a different opinion, and yes Tim, like me, is entitled to his opinion.
And yes, I think that Tim does have good knowledge of electronics, but I am not crazy either.

Please understand:

I don't give a shit about opinions.  My opinion doesn't matter.  Nor do other's.  Brains conflate or fabricate all sorts of things.  Brains filter everything through their own experiences.  Everyone's opinion is so different as to be useless noise.  And that is why, as they say: "talk is cheap".  Because it's not worth anything.

What I'm after is hard data.  Numbers.  Measurements.  Facts.

Instruments don't lie.  They might be connected wrong, they might be set wrong, but once all of those factors are determined, there can be no lie.

I mean no offense by my frankness.  I just don't find pleasantries useful.  Circuits certainly don't care; you can stick them with a burning hot soldering iron and they beg for more.

HTH,
Tim

[BravoV]

I am from XXXXX in the ZZZZZZZZ, that means that I am direct and do not lie , and no bullshit.

For you actually its never about electronics, its all about attitude, and pretty bad one. 

[BravoV]

I mean no offense by my frankness.  I just don't find pleasantries useful.  Circuits certainly don't care..........

This  , which my self and also believe a lot of others here looking at their responses to you, don't mind at all, and I have learned a lot from you here in this forum, thank you.   

[exe]

Guys, please be polite and respectful to each other.

Concerning PSU, there are tiny bits that could be done differently, but who cares? Final performance is that matters. Also, as I understand, each building block was comprehensively evaluated. So, I guess, if I start substituting components it's not granted I'll get the same performance (quite likely the opposite). No offence, but I think not everyone knows/understands/appreciates how much effort was put into design of this PSU (I know this because I read that circuitsonline.net thread, as well many others to better understand this circuit). Because it's so popular, people like to challenge this circuit, but not always with enough respect, imho.

It's that I'm defending blackdog (although I would), it's my personal opinion based on my personal experience in designing power supplies (I designed 4 or 5 of them, all garbage, to be honest). That's why I'm looking for a good not-too-overcomplicated PSU that I could "enhance" with an MCU .

Aaanyway, it's time for silly questions   Is a separate isolated power supply needed? Can I just use a charge pump to generate some voltage above the output? Let's say I can sacrifice some noise performance (my PSU enclosure is not shielded (plastic), so I'm not going to get microvolts of noise even if I try hard).

[Cerebus]

While we're on the subject of testing PSUs with step loads: A while back I was comparing specs of a bunch of bench power supplies on the typical 50% to 100% current load step recovery time test. The reason for this was to develop a set of target test specifications for a PSU I was designing. What was conspicuous by its absence in those specs were specified slew rates for the waveform of the applied test load.

What I'd found testing my own design in simulation was that I could get as stable as I liked but if I went to too fast an edge for the test load then it would (kind of obviously) all go to hell in a handbasket. So I wanted to know what slew rate was reasonable to test against. (Obviously in simulation I was able to apply physically improbable/impossible edge speeds.)

So, the question is: What is a reasonable slew rate for an applied step load when testing PSU regulation recovery times? Are there industry standards? (I couldn't find evidence of any.) Or do people just test with whatever slew rate the electronic loads available to them support?