Just ignore that 10nF|100nF bullcrap even if it seems to come from a reputable source. SRF is meaningless, only as low as possible supply impedance over as wide as possible frequency spectrum matters, and you get that by using largest possible value of C in smallest possible package (minimum ESL).
Paralleling two different values starts to matter when you need so much C that you need to go to large package size and place that further away.
10nF|100nF hardly ever makes any sense because you can get the 100nF cap in the same package (smallest you can handle, likely 0402 or 0201 if you feel like it) as the 10nF cap, and can place the single chip in the prime spot right next and between the power pins.
10nF cap would have SRF at higher frequency but if you look at the absolute value of Z, it will be roughly equal at that SRF for the two parts (despite 100nF parts being "over" SRF). In other words, the 10nF and 100nF MLCCs perform the same at high frequencies, but 100nF performs better at low frequency side. Obviously, paralleling two parts at all improves the things, especially if you are adding more vias while at it. But they could have been just 2 x 100nF for simpler BOM, and avoiding risk of oscillations which are sometimes seen when paralleling different MLCC values.
But the AD's picture really explains it all: the 100nF part is drawn physically larger than 10nF, go figure. So in this fabricated example, paralleling the parts can be beneficial, but the actual solution would have been to just use a 100nF part in that 10nF footprint.
The concept is valid, and paralleling a 4.7uF tantalum in 1206 with 100nF MLCC in 0402 makes perfect sense and is done with the AD example layout, but the devil is in the details, and the fact you should go 1000km/h with an airplane does not mean you should go 1000km/h with a car.