I've got this old (Sanmina1 MV 1) LCD module I salvaged from an old II Morrow Tigershark Loran of some sort.
It uses two Hitachi HD61602 chips and a 74HC00 (two NAND gates are connected to the CS pins of the HD61602s).
http://www.pacificdisplay.com/ics_app%20notes/hitachi/HD61602-61603.pdfIn the datasheet is says this about the READY pin...
READYNumber of lines:1 / NMOS open drain output / Connected to: MCU
While data is being set in the display data RAM
and mode setting latch in the LSI after data
transfer, low is output from the READY terminal
to inhibit the next data input.
There are two modes: one in which low is output
only when both of CS and RE are low, and the
other in which low is output regardless of CS and
RE.
3. READY output mode
Determines the READY output timing.
After a data set is transferred, the data is processed internally. The next data cannot be acknowledged
during the processing period. The READY output reports the period to the MPU. The timing when the
READY is output can be selected from the following two modes:
a. READY is mode always available (Figure 12).
b. READY is mode available by CS and RE (Figure 13).
QUESTION?
Is this pin simply there to give the MCU a warning that it should only send data when it sees this pin is high?
I know this is ancient hardware but I'm just seeing if I can figure it out.