Ethernet bit rate

[joniengr081]

The Ethernet bit rate which are common these days are 1 Gbps and 10 Gbps. The question is how do we relate Gbps to the clock frequency of the digital signal and time period. For 1 Gbps the digital signal is itself 1 GHz or 500 HMz ?

[redkitedesign]

Depends on the physical interface. Wikipedia has a lot of information:
https://en.wikipedia.org/wiki/Ethernet_physical_layer#1_Gbit/s

In short, it can be 62.5MHz, 125MHz, 625MHz for 1G, and pretty much everything between 800MHz and 13.7GHz for 10G.
I personally like 9.95328 GHz, since I started 25yrs ago on STM64 optics using that rate :-)

[joniengr081]

Please explain how this can be 62.5MHz, 125MHz, 625MHz for 1Gbps. By clock frequency I mean cycle per second measured in Hz. There can be 2 bits per Hz, that way I assume 500 Hz for 1Gbps but I don't understand how it can also be 62.5MHz, 125MHz, 625MHz for 1Gbps.

[Berni]

Ethernet is not just digital 1 or 0 (apart from the ancient BASE10).

Multiple voltage levels and encoding is used to purposely reduce the required frequency bandwidth, so that long cable runs can better handle the speeds.

[m k]

It can be modulated.

https://en.wikipedia.org/wiki/Pulse-amplitude_modulation

[radiolistener]

The Ethernet bit rate which are common these days are 1 Gbps and 10 Gbps. The question is how do we relate Gbps to the clock frequency of the digital signal and time period. For 1 Gbps the digital signal is itself 1 GHz or 500 HMz ?

GMII Ethernet interface uses 125 MHz clock x 8 parallel bits. If you're asking for physical media, it's not like serial transmission, it uses quadrature (QAM modulation), where both - amplitude and phase are used to encode symbol, so it sends entire symbol (several bits) over media at once. Some symbol codes are reserved and don't used for usual data transfer.

But all that things with modulation/demodulation, link negotiation, signal power adjustment, error correction and other things are done in GMII PHY chip, which is just provide you with 125 MHz x 8 bit parallel bus, so you don't care how it's encoded on the physical media.

So, the answer on your question is 125 MHz * 8 bit = 1000 Megabits per second. Full Duplex link allows to transfer 1000 Mbps in both direction simultaneously, and the the total bandwidth of the media will be 2 Gbps.

Also note, that these 1000 Mbps is not a max speed for data transfer, because you're needs to send packet preamble, address and CRC for every data packet, so it consume some part of full bandwidth. Using large packets (they named jumbo packets) allows to reduce overhead costs, so you can use higher data transfer rate by using jumbo packets, but usually they are not accepted by default and system needs to be configure in order to receive jumbo packets.

[radiolistener]

Please explain how this can be 62.5MHz, 125MHz, 625MHz for 1Gbps.

The stream is 125 MHz x 8 bit. But it can be transfered in different way, for example you can transfer 8 bits on rise edge of clock, or 4 bits on rise edge and 4 bits on fall edge. 4 bits transfer allows to reduce data lines, but it needs more strict timing requirements because it uses double data rate through each data line.

I didn't hear about 62.5, 625 and 1000 MHz. Usually GMII PHY has 125 MHz clock and can be configured for 4 bit DDR or 8 bit SDR transfer.

[Berni]

I didn't hear about 62.5, 625 and 1000 MHz. Usually GMII PHY has 125 MHz clock and can be configured for 4 bit DDR or 8 bit SDR transfer.

These frequencies are the occupied bandwidth on the copper wires. Not the actual data rates.

For the trusty old 100BASE the 100Mbit of actual digital bandwidth is packed into a symbol rate of 125MBaud (data rate goes up due to the 4B5B encoding method) but then uses 31MHz of frequency bandwidth on the wire due to using MLT3 modulation. This way it is well within the rated 100MHz bandwidth of CAT5 cable.

For the popular 1000BASE the 1Gbit is packed into a symbol rate of 125MBaud on 4 twisted pairs. But instead uses PAM5 modulation to pack enough data into the low baudrate. This requires a higher frequency bandwidth of 62.5 MHz on the wires, but is still within the 100MHz rating of CAT5

The 625MHz i have no idea where you got that from. Perhaps the 10GBASE where it packs 6.25 bits per Hz of bandwidth giving you 10Gbit using 4 pairs doing 800Mbaud and occupying 400MHz of bandwidth, so within the 500MHz rating of CAT6

[joniengr081]

Thankyou very much for reply. I was not aware about the modulation but now I think the concept is clear to me.

I am familiar with 1Gbps (1000BASE) in which there are two x differential pairs and two Rx differential pairs. Two differential pairs on each way can make four different symbols and because of DDR, there will be 8 bits, so the digital signal on the Tx and Rx will be 125 MHz for 1Gbps (1000BASE). The Ethernet connector RJ45 have four differential pairs, is compatible with 100 Mbps and 1000 Mbps. Which connector and pinout is for 10 Gbps ? The digital signal on 10 Gbps is of which clock frequency

[mariush]

100 mbps only needs one rx and one tx pair (4 wires). gigabit and up needs all 8 wires.

Maybe this Wikipedia article will help, when it comes to 10 gbps : https://en.wikipedia.org/wiki/10_Gigabit_Ethernet

and this page also has details about the latest additions 2.5g and 5g modes : https://en.wikipedia.org/wiki/2.5GBASE-T_and_5GBASE-T

The article has a link to a PDF with details about the modulation used:

10GBASE--T Coding and Modulation:T Coding and Modulation: 128128--DSQ + LDPCDSQ + LDP: https://grouper.ieee.org/groups/802/3/an/public/sep04/ungerboeck_2_0904.pdf

[radiolistener]

Two differential pairs on each way can make four different symbols and because of DDR, there will be 8 bits, so the digital signal on the Tx and Rx will be 125 MHz for 1Gbps (1000BASE).

No. You're confuse physical medium and GMII PHY interface.

GMII PHY interface is a data lines between your CPU/FPGA (MAC) and GMII PHY chip, it always have 125 MHz 8 bit, but these 8 bits can be transfered through 4 data lines with DDR or with 8 data lines with SDR. This is configured when device is designed.

Physical medium is a different thing. This is environment through which actual transfer of data is done. It can be twisted pairs or optical fiber, or RF spectrum, etc. For example, you send some data to a GMII PHY as 8-bit 125 MHz stream, GMII PHY encode it into symbols and send that symbols with PAM modulation through differential pairs to a remote link point, remote link point GMII PHY receive it and decode to a 8-bit 125 MHz stream and put to CPU/FPGA for further processing.

[joniengr081]

Yes, there are two interfaces in 1000BASE.

Between CPU/FPGA and GMII PHY chip, there are four Tx and four Rx lines. With DDR it will be 8 bit 125 MHz interface that will make 1 Gbps each way, right ?

Between GMII PHY chip and the PCB connector RJ45, there are in total four pairs, two pairs for Tx and two pairs for Rx. I am wondering which digital signal frequency we have on this interface.

[radiolistener]

Between CPU/FPGA and GMII PHY chip, there are four Tx and four Rx lines. With DDR it will be 8 bit 125 MHz interface that will make 1 Gbps each way, right ?

No.
CPU/FPGA side is named MAC (media access controller).
PHY is a physical layer.

Between MAC and PHY there is always 125 MHz 8-bit stream. But this stream can be transferred with DDR through 4 data lines (by using both clock edges it result to a 8 bits). Each PHY endpoint has two streams - RX and TX, each 125 MHz 8-bit.

Next, between two remote PHY the link is established through some medium such as twisted pair or optical fiber. It uses pulse-amplitude modulation to send symbols over medium. In such way RX and TX streams are encoded into symbols and send over medium to the remote PHY endpoint, remote PHY endpoint decode it to TX and RX stream for MAC.

Between GMII PHY chip and the PCB connector RJ45, there are in total four pairs, two pairs for Tx and two pairs for Rx. I am wondering which digital signal frequency we have on this interface.

it sends symbols through all 4 pairs, this is not a digital signal, but analog one because it has more than 2 amplitude levels. I don't know how it is encoded on a pairs, because PHY chip doing all job to encode and decode it, so there is no need to deal with it.

[redkitedesign]

Between MAC and PHY there is always 125 MHz 8-bit stream. But this stream can be transferred with DDR through 4 data lines (by using both clock edges it result to a 8 bits). Each PHY endpoint has two streams - RX and TX, each 125 MHz 8-bit.

GMII is a 8 bit, 125MBaud stream. The clock is 125MHz, the base frequency of the data is 62.5MHz
RGMII is  4 bit, 250MBaud stream. The clock is still 125MHz, but data is transferred on both edges, thus the frequency on the datawires is twice as high, 125MHx.
SGMII is a 1 bit, 1250MBaud stream. The clock is 1.25GHz, but ususally not sent seperately. There is and extra 4B/5B encoding added to ensure enough edges in the datastream to recover the clock. The base frequency of the signal is thus 625MHz.

But this is all board level signalling, no sane person will try to transmit (R)GMII over any distance. SGMII can work, as it is very similar to 1000BASE-TX (1GBit ethernet over fiber). Just the autonegotiation details are different.

it sends symbols through all 4 pairs, this is not a digital signal, but analog one because it has more than 2 amplitude levels.

Its still digital. Its not binary, but still discrete in both time and amplitude.
On the other hand, to do anything useful with it you'll have to watch the bandwidth, noise and attenuation of the link so you might as well treat it as an analog signal.

[joniengr081]

Thank you very much for reply. Now I understand the interface between MAC and PHY that there is always 125 MHz 8-bit stream in 1Gbps (1000BASE). There are four Tx and four Rx that makes 8 bits with DDR. 

Now I would like to understand the interface between two remote PHY.

Let's suppose there is a ZYNQ SOC development board having MAC implemented on the ZYNQ SOC and a PHY chip on the development board. The ZYNQ SOC support 1Gbps (1000BASE). There are four differential pairs on the PCB between PHY and Ethernet connector. Two for Tx and two for Rx. I am interested to understand this signal interface.

I also understand that it uses pulse-amplitude modulation to send symbols over copper traces to the Ethernet connector.

The symbols send are not digital signal, but they are analog and may have more than 2 amplitude levels, right ? Let's not go in to encoding scheme to keep things simple. Please correct me if anything I wrote is wrong.

Now what about if the link is 10 Gbps instead of 1 Gbps. How many Tx and Rx lines between MAC and PHY in 10 Gbps Ethernet and what is the frequency and how many bits (like we know it is 8-bit DDR 125 MHz consisting for four Tx and for Rx in case of 1 Gbps). Any is it still analog phase amplitude modulated between the PHY and the Ethernet connector on the copper traces on PCB ? How many pairs signal have between PHY and the Ethernet connector on the PCB. It is still RJ45, maybe not.

[redkitedesign]

Thank you very much for reply. Now I understand the interface between MAC and PHY that there is always 125 MHz 8-bit stream in 1Gbps (1000BASE). There are four Tx and four Rx that makes 8 bits with DDR.

Nope, its either 8 bits TX, and 8 bits RX, and called GMII. Or 4 bits TX, 4 bit RX, and called RGMII. DDR is either memory or a former communist country in Eastern Europe.

Let's suppose there is a ZYNQ SOC development board having MAC implemented on the ZYNQ SOC and a PHY chip on the development board. The ZYNQ SOC support 1Gbps (1000BASE).

Don't know what your talking about 1000BASE. It does not exist.
There is 1000BASE-T, which is probably what you mean. (1G ethernet over Cat5e (or better) cable, using RJ45 connectors. This is explained in the Wikipedia page linked in the first reply of this thread)
There is 1000BASE-SX, which is 1G ethernet using 850nm light over short (550m) multimode fiber lengths (and what is probably the most common 1G ethernet over fiber spec)

And there are a lot of other 1000BASE-xxx variants. All different, and more importantly, all different signalling specs!

There are four differential pairs on the PCB between PHY and Ethernet connector. Two for Tx and two for Rx. I am interested to understand this signal interface.

Nope. All four are for TX, and all four are for RX. And they dont go to the connector, they go to the magnetics (which might be integrated in the connector, so you cannot see them). And the magnetics are really important!

1000BASE-T uses the same trick as old analog phone lines: The signal on the wire is TX+RX. The receiver knows what the transmitter is transmitting, and can substract it from the signal on the wire.

Thus all 8 wires are used for transmission, and reception, at the same time!

I also understand that it uses pulse-amplitude modulation to send symbols over copper traces to the Ethernet connector.

The signal on the copper traces to the connector is the same as the signal on the wire. (There is some difference in voltage etc between the PHY to Magnetics signal and the Magnetics-core-wire signal, but otherwise (shape, frequency, information content) they are exactly the same)

The modulation scheme is called PAM5, which is kind of a misnomer as there is nothing analog in the actual ethernet signal.

The symbols send are not digital signal, but they are analog and may have more than 2 amplitude levels, right ?

They are digital. The signal is 5-level, but only those 5 levels. An analog signal would use any and every level between minimum and maximum.
And there is no simple mapping from the bits in the original datastream to the levels on the wire, because there is an 8 bit to 10 bit mapping, and a Trellis encoding done in the PHY. This all improves signal quality.

Now what about if the link is 10 Gbps instead of 1 Gbps.

Check Wikipedia. Or IEEE802.3, its free, and its all in there.

[radiolistener]

They are digital. The signal is 5-level, but only those 5 levels. An analog signal would use any and every level between minimum and maximum.

in such way we can say that the output of 24-bit DAC is also digital, because it has only 16777216 levels

As I understand, term "digital" describes systems that generate and process binary data. So, if it generates signal which is not binary, then it's not digital.

The signal with 5 amplitude levels cannot be generated with digital logic gates. There is needs Digital to Analog Converter (DAC) to do that, isn't it?

[redkitedesign]

They are digital. The signal is 5-level, but only those 5 levels. An analog signal would use any and every level between minimum and maximum.

in such way we can say that the output of 24-bit DAC is also digital, because it has only 16777216 levels

Yes we can. And the difference between the intended analog signal and the output of the DAC is called quantization noise.

As I understand, term "digital" describes systems that generate and process binary data. So, if it generates signal which is not binary, then it's not digital.

By that logic, text is analog since there are 26 letters, and thus its not binary.

A much more useful differentiation is discrete versus continues. If there is a limited number of allowed levels, its discrete/digital. If any level is allowed (and considered different from any other level!), it is continues and thus analog.

[radiolistener]

Yes we can. And the difference between the intended analog signal and the output of the DAC is called quantization noise.

No, we can't, since digital signal is converted to analog one with DAC, it is no more digital, but analog.

The difference here is that it doesn't represented with discrete 1 and 0 levels with discrete points in time at clock edge, the DAC output has infinite continuous spectrum and continuous amplitude. Even if DAC has just 5 levels, the output can have infinite count of levels between these 5 levels.

Technically digital signal is also represented with analog signal. But since it represents discrete amplitude 1 or 0 and discrete points in time determined by a clock edge it can be assumed as digital.

The reason why all 4 pairs are used for TX and RX simultaneously is that the signal here is analog, not digital. The digital signal cannot support transfer in both direction simultaneously through the same wire. It is possible for analog signal, because receiver knows what is the current transmitter level and what is the phase delay and can use analog substraction to remove it for further processing.

Since this is not digital signal it also cannot be processed with a digital gate input, it needs ADC to convert it from analog to a digital domain.

[Siwastaja]

The difference here is that it doesn't represented with discrete 1 and 0 levels with discrete points in time at clock edge

What you describe is synchronous binary signal.

I know, in everyday speech everybody says "digital" when they mean "binary", but every once in a while you find academic coffee discussions like this and you ought to be careful.

Multi-level signals are often called digital signals; probably a significant distinction being ability to correctly interpret those levels later on (practically impossible with 2^24 levels, of course).

[radiolistener]

By that logic, text is analog since there are 26 letters, and thus its not binary.

it depends on what you're mean when talking about "text".

If you're means binary encoding of letters where letter is represented with bytes and every byte is represented with a set of 8 binary values, where every binary value is represented with 1 or 0 value, then such a "text" is digital.

But if you're means text as existing letters on the paper, where each letter is unique due to a paper roughness and uneven ink color, then such a "text" is not digital, but analog. This is because digital text is converted to analog text during printing and since it's converted to analog text, it is no more digital, but analog one

[radiolistener]

I know, in everyday speech everybody says "digital" when they mean "binary"

This is because almost all digital electronics uses binary logic. Other kind of logic is also possible, for example there is possible ternary logic. But in practice it's not used because it's more complicated than a binary logic and used primary in math analysis. This is why the term "digital" is used for signals which can be represented and processed with a binary logic gates.

If you want signal which is represented from more than two levels, there is needs conversion between digital (binary) signal to analog (multi level) signal. Such conversion can be done with DAC and ADC.

[Siwastaja]

I know, in everyday speech everybody says "digital" when they mean "binary"

This is because almost all digital electronics uses binary logic. Other kind of logic is also possible, for example there is possible ternary logic. But in practice it's not used because it's more complicated than a binary logic and used primary in math analysis.

Yeah, don't see multilevel everyday, but right now the discussion is about a thing which does not use binary but multi-level, namely Ethernet. Not logic, just 1:1 communication preserving the data, but why would that matter if we want to be autistic about terminology.

[radiolistener]

Yeah, don't see multilevel everyday, but right now the discussion is about a thing which does not use binary but multi-level, namely Ethernet.

It's happens that the term "digital" is applied to a binary signal representation.

Did you ever seen DAC or ADC with a digital interface which is not binary and has multi-level amplitude on digital input/output?

Regarding to the signal on ethernet pairs, it is 100% analog, because it may have infinite count of levels despite the fact that it is generated with DAC that has just 5 discrete levels. This is why analog operations is used on that signal in order to make possible two way transfer through the same pair simultaneously.

And there is not just 5 levels on Ethernet pairs, because Ethernet PHY can tune amplitude of the transmitted signal in order to get the better SNR level. In addition ethernet pair signal also has a signal echo due to reflection from the receiver endpoint. So, this is very complex analog signal.

[m k]

Back in the day 10M Ethernet segment had a max. length of 185m.
Not because of attenuation or anything like that, it was for collision detection, shortest packet must reach all parts of the segment.
It has not changed, basic function is still there and so upgraded away, and so current 100m cable limit is something else but still something.