Driving shift registers and transistors from FPGA out pins

[alpines]

Hello there, electronics newbie here.

I've spent the last few months on and off writing VHDL code to drive a i2s sound module and a selfmade LED board from my Digilent Basys3 which has an Xilinx Artix 7 35T on it.
The FPGA dev board streams encoded media from the onboard flash, decodes it and plays it back on the audio and video modules.

Unlike the sound module, I wanted to make the LED matrix myself, I especially wanted it to be made out of discrete 5mm LEDs (Uf=3V, If=30mA).
My initial plan was to drive one of these Charliplexing Arduino LED shields, but I've ditched them since I needed something bigger.

So I've tried to come up with a design and scaled it down to 8x6 pixels (instead of the desired 32x24 pixels) to start prototyping.
Well, now that I actually have the small board soldered on a veroboard I think I need to fix up the design before moving further--but it actually works!
You can find the schematic in the attachments.

Some things to keep in mind before reading the following questions:
- The bigger version will be soldered on a PCB for which the layout doesn't exist yet
- The board receives it's power currently from a variable DC power supply set to 5V/1A
- The LEDs are being driven by multiplexing the rows. I know this will have a toll on the brighness of the bigger board, but this is a non-issue
- The different brightness is achieved by strobing the current frame and turning the transistor on if it's above a certain threshold (basically PWM)
- This is a first for me and I had little knowledge before starting this project about electronics (especially part selection and protection)
- The two shift registers for the row selection are intentional to simulate multiple shift registers concatenated on the full board
- The IRLZ44N seemed like a good choice to handle the low-side switching (and it fits on the veroboard) but is probably overkill?
- The IRF4095 was the only choice that I found because of the availability at that time, I know this is overkill. I needed a high-side switch to deliver at least 1A at 5V Drain/Source.

There are a lot of questions I couldn't find a good answer to and hopefully you guys can help me out.

I've tried driving the matrix with my FPGA from the PMOD header JB and manage to clock ShiftRowDataIn_n (which is the fastest toggling line in my case) with almost 100 kHz.
The picture is good, the registers and the selfmade logic level shifter seem to do the job just fine but if I probe the drain of that level shifter transistor I can see that it barely charges up enough to be registered appropriately for the 74HC595s.
This was after I changed up the Pull-Ups from 10k to 1k for each path. Before it barely managed to hit 25 kHz.
I saw that I can go faster than that if I reduce the resistor values even further (not only the pull ups, but also the gate resistors) but I thought I may end up frying something, needless to say it also draws a lot more power when the transistor is on and all the current through the pullup goes to ground.

In a lot of articles (wiring them up to Arduino outputs) I read that a gate resistor is used to limit the current going into a MOSFET gate to charge up the capacitance between source and gate, otherwise the transistor may end up pulling too much current and the device supplying the current can break.
Since this would be my FPGA I was very cautious about this.
Do I really need that 1k gate resistance to protect my FPGA? Don't they significantly reduce switching speeds? This question is also for the same resistors in front of the low-side/high-side transistor gates.
I feel like I'm missing a very core information here on when to use these and when not to, after all the shift registers' inputs for example are pulled directly to GND not "softly" through a resistor.

There is also a rule of thumb out there to add a 100nF ceramic cap close to every IC's VCC/GND to dampen the voltage drop when the IC switches and pulls current.
Does this only apply at certain speeds, or is this a general necessity because it only happens to occur more often at high speeds?

While I'm happy that this prototype works, I've calculated that I need at least 16x the switching frequency (going from 8x6 to 32x24) or around 1.25 MHz.
I figured I can lower this number to a quarter by splitting up the data feeding onto four data lines, this doesn't solve my problem but it helps a bit.
From my understanding, this method of level shifting is not really suitable for these kinds of speeds, and apparently popular level shifters like these from SparkFun with a BSS138 are also too slow?
How to I transfer my 3.3V signals from my FPGA to the 5V shift registers with up to 1-2 MHz? The 74HC595's datasheet says it needs Vih=3.15V for 4.5V (Vih for 5V > 3.3V?) so wiring them up directly sounds like it will not work reliably.


And finally: If you have general recommendations, improvements or constructive criticism I'd love to hear them. This is my first electronics project, and I am very happy with the software and HDL side of things, but the hardware design I cannot judge. I'm sure there are a lot of things I could have done better, especially in regards to part selection so let me know!

If anything is unclear please ask, I'll try my best to answer them.

[langwadt]

use 74HCT595 instead, Vih is only 2V

[alpines]

Excellent suggestion, seems like this will eliminate the level shifters altogether. I will certainly get a few of those.

Meanwhile I did further research and took a look at the Basys3 schematic to discover that it already has 200 Ohm resistors on all of the PMOD JB data lines.
That is excellent as I can drive the shift register directly without additional slowdown, hopefully achieving my target frequency.

However a few questions remain, and I'd be glad if these could be answered aswell:
- Do I need to protect the shift register's output from the N-MOSFET inrush current with a series resistor?
- Does the inrush current not matter if the gate/source capacitance is low enough? If so, what is considered low enough?
- Are 100nF ceramic caps on an ICs VCC/GND only necessary above a certain switching speed or is this a general necessity but it occurs more often at high speeds?
- Even though I got rid of the level shifters, how would one go about level shifting from 3.3V to 5V or above for speeds up to 1-2 MHz?

Thanks in advance!

[xvr]

Use TPIC6A595 for lower side switches. It has 350mA current capability, I hope it will be enough. So you can get rid of all IRLZ44 mosfets.

Do I need to protect the shift register's output from the N-MOSFET inrush current with a series resistor?

It highly desirable, but 1K is overkill. It should limit current to maximum allowed for output (pulsed mode).
74HC595 has maximum current of 35mA, so resistor should be about 140R.

Does the inrush current not matter if the gate/source capacitance is low enough? If so, what is considered low enough?

Power MOSFET has significat gate capacitance. So resistor highly recomended. Without resistor surge current of gate charge will be limited only by output mosfet inside IC. It will survive, but it could reduce service time and raise surges on power line.

Are 100nF ceramic caps on an ICs VCC/GND only necessary above a certain switching speed or is this a general necessity but it occurs more often at high speeds?

Always, and ABOSULTELY mandatory.

Even though I got rid of the level shifters, how would one go about level shifting from 3.3V to 5V or above for speeds up to 1-2 MHz?

https://www.digikey.ie/en/products/filter/translators-level-shifters/732?s=N4IgjCBcpg7AbAJiqAxlAZgQwDYGcBTAGhAHsoBtEAFjgQFYQBdEgBwBcoQBldgJwCWAOwDmIAL4kwATjARoIdJGz5iZSjUQAGMPFjM2nSD37Cxk8LIDMKRZlyES5SFS0A6ABwACAGpeAfl5WbvC%2BICTu0r4BQSFhEW5RfoH0bvTx4NGBYG5WGWBZsaE%2B4eBuWt7JXjnSlaU5FYWp6SVSbgVVwcX17U1p%2BW6IfS098C0xXQNjwwOVMYhusBkLeVXNGasxYCMkm9l1LCAcXABKWKIEAKpCAuwA8hgAsgRYeACufAQSUrLUtkoqRzqFwgSIzVplRprfoQnIdGLrWGDcGjcYpGGlFYo3aFbYbXEHQync4iK43e5PF7vT7fSweaT-eyqJwaLTMCwAWmQCiU-DeamcVEYTE5DJ5UD5Ao0EBFFm5VBwBAAbgQcF48AALAQYdgEPjsoA

TXU0104 for example

[alpines]

Interesting, so bascially the TPIC6A595 would accomplish what the IRLZ44 and the 74HC595 do together.
But from the datasheet I see that the logic levels would be incompatible. Vcc = [4.5V, 5.5V] and Vih,min = 0.85*Vcc so I would still need to add a level shifting circuit in front of it like the one you proposed or am I missing something?

On a sidenote: Sinking 350mA is definitely enough as there should be only one row active meaning each drain would need to sink ~30mA but(!) if by accident all rows light up, that would result in 24*30mA = 720mA through each output.
Granted this is a fault case, but would it make sense to size my components in such a way, this will not break anything or is this OK aslong as the HDL for it isn't broken? I'd say for a hobbyist circuit, this probably doesn't matter too much.

[xvr]

o I would still need to add a level shifting circuit in front of it like the one you proposed

Yes, level shifter is required. BTW - you can use any 74HCT series logic as level shifter - it has 2.4V input level, but full plain CMOS output levels.

[alpines]

This sounds very convenient, I'll be sure to save this info in the back of my head

I wanna stick with six lines from the FPGA to the board (but will change the semantics a little bit) so I came to the conclusion that a 74HCT367 Hex Buffer can do the job of shifting the logic levels.
Now I don't think I need to put resistors inbetween the buffer and the shift register but I have no idea why this is the case here.

About the high-side switching: Is the structure there more suitable as it is because the transistors there need to drive 1A peak?
These also need to switch way slower, so I think even though there are better transistors (and I want to look for different ones), they should work just fine.

[xvr]

Now I don't think I need to put resistors inbetween the buffer and the shift register but I have no idea why this is the case here.

Hmm. There are no resistors there in your schematic.

BTW, you can replace U2 & U3 and level shifter (Q18-Q20) by 3-to-8 decoder IC (74HCT138)

[alpines]

Yes, and I have no idea why I can't understand when to really limit input/output currents, this is a mystery for me.
You limit the output current of a shift register to save it from killing itself charging up the gate/source capacity of the MOSFET.
But do you need to limit its input because it could draw too much killing something in itself? Why can you connect two 74 logic gates to one another and not worry about this? Are they current limited inside the IC already?

Anyway, changing to a 3-to-8 decoder would work in this case, but I think I'll stick with the buffer idea, the main reason being on how I want to drive the matrix.
I was thinking of splitting up the matrix into two distinct circuits to minimize the brightness loss and had a shower thought that I could achieve this by merging the ApplyRowData and ApplyRowStrobe lines.
This gives me a free line to feed in another RowDataIn signal saving me clock cycles I could use to strobe the picture more often. With an octal buffer I could even quadruple it maxing out a full PMOD port.
I should modify my VHDL code a bit to simulate and test these brightness levels to see if this is the way.

Also, the decoder can supply +-4mA of current which I'm worried is not enough to drive the high-side switches fast enough.
Probably not the IRF4905 but, maybe another more suitable one.

[xvr]

> But do you need to limit its input because it could draw too much killing something in itself?

You don't need any current limiting resistors here. You can directly connect any output of 74HC series to its input. Input capacitance of it very small (compared to power MOSFET gate), so internal resistance of IC output will be enough to limit charge current.

[alpines]

One final question: Is there a general rule or something to determine when the capacitance is so high, that resistors should be considered and when not?

[xvr]

Stray capacitance of IC input generally stays in range 6-12pF. IC output of average IC can be connected to ~10 inputs. So capacitance less than 150-200pF can be considered as neglectiable. Capacitance above 1nF required attention.
This is true for general circuit - frequncies up to 100MHz, logic level signals.
Analog circuit and high speed (1GHz and more) required attention to all stray elements, whatever value they be.

[alpines]

Awesome, thank you very much. Your help has been invaluable and I've learned a lot!