So I got some progress
First I wanted to make sure I could see an image out of the composite output of the SuperScan2 so I programmed the DE0-Nano so it will boot to the VGA pattern posted earlier, power it with the TV USB (Service) plug and feed the Composite input from the converted VGA to NTSC.
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97719;image)
Then I took it back to my office and started to probe the FIFO chips.
The Write Clock WCK runs at 25.125MHz, this is what is used to store the data from the 6 bit per color ADC chip into the FIFOs.
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97721;image)
The Read Clock RCK runs at 12.690MHz, a bit faster than half of the Write clock.
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97723;image)
The reason for this is that the Write Enable is double buffered so it writes half to the odd chips and the other half to the even chips.
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97725;image)
The SuperScan2 specs talk about 32bit color, but it really only supports 5/6/5. The ADC is only 6bits per color and they don't use R0 and B0, only the Green channel uses all 6 bits, making it a 16 bit decoder.Now since they double buffered it, it really is using 32bits, tricky bastards.
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97727;image)
The output buffer (above the top inputs and below the bottom inputs) are read at half the frame rate all four chips at the same time, so the odd chips will have the odd field and the even chips will have the other half of the data.
This is what DO1 (Half of R2 output) looks like in a single frame at 60Hz
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97729;image)
This is a closeup of a single line of DO1 (Half of R2 output) so it flips 16 times for every 256 analog outputs (what you are seeing there is 640 so 256+256+128)
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97731;image)
Looking at the green channel that uses all 6 bits, cycling from 0 to 255 will cause the inputs to flip these many times per color bit.
G5 2 times
G4 4 times
G3 8 times
G2 16 times
G1 32 times
G0 64 times
Now I have some soldering to do. Not sure if I'm going to solder directly in the inputs or the outputs. Using the inputs I can use only 16 wires for the RGB 5/6/5 Then use the Write Clock (one common pin) and Write Enable for each bank (two pins) The DE0Nano would not have any problems dealing with a 25MHz input clock from the chip. Also I can probably solder R0 and B0 to get the full 18 bits RGB 6/6/6. Total pins used 21. I will have to make sure I use a pin for the Write Clock that supports external clocks.
The sync signals will already be in the FPGA since i'm going to pass the composite as an input (treated as binary) to extract the HSync and the VSync to feed into the SuperScan. It should not add too much delay compared to the original timing. This will add three pins for a total of 24 GPIOs.
If the FPGA adds too much delay then I will have to use the LM1881/74LS221 to get the VSync and HSync by hardware using pin 4 from the Saturn connector to get the 5 volts needed for the chips.
Like this:
![](https://www.eevblog.com/forum/beginners/converting-15khz-analog-rgb-to-digital/?action=dlattach;attach=97733;image)
Now to solder and write some code for the capture. I think I'm going to just tap into the inputs since the FIFO buffers don't give me anything that I need since I will have to use twice as many cables to get 16bits color instead of 18bits color.
Edit: I take it back the FIFOs give me a nice place to solder my 40 pin connector into the input signals and the clock plus write enable
![Smiley :)](https://www.eevblog.com/forum/Smileys/default/xsmiley.gif.pagespeed.ic.R8GFI-pF6f.png)
Edit: I just noticed the Read Clock is 5 volts, so that seals the deal to use the input signals and forget the FIFO buffering. Write Enable is over 3.3V (around 4V) so I will have to deal with that too.