I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?
I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Yes, certainly, transistors are the basic element. But, actually, there is a lower level, which is the individual layer masks.
Will the same be applicable for digital circuits?
Yes, at the lowest level, it is all analog, and all transistors, resistors and wires.
2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
Yes, you must select a process first, to have the parameters of the silicon, doping, etc. before you can start describing the transistor channel width and length.
Each transistor is described by length, width and type (doping). Each process has a "design kit' which has all these specs.
3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
You really CAN'T! These are proprietary parts, and TI, etc. will not give out the internal design. So, you have to redesign these parts in the process you select.
Then, simulate until the performance is what you want.
4. What tools are required for creating and sending the designs to mask maker and foundry?
There are several major programs. If you are not at a university, the commercial design suites are very expensive, like 50K US dollars/seat, with massive costs to renew each year. Cadence is the leader, Mentor is still used, I think. There are also some open-source design packages.
5. What are the costs and MOQ involved in the whole process?
I am involved in a university project making chips for nuclear physics experiments. We use MOSIS, and a university Cadence license. We used to use the AMI (now ON Semi) C5 process, a 350 nm 5V process. We just did our first chip with the Austria Semi (AMS) fab. Their design kit is WAY better than the AMI/ON Semi kit. Minimum order is 40 parts (untested) and you can order more in 40-part increments. Our chip was fairly large, about 5 x 7 mm, and the cost for 40 parts would run some $28K US dollars, unpackaged. They usually charge something like $7500 for packaging.
6. I have heard of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?
Well, MOSIS combines dozens of masks from different projects onto one wafer, and thus spreads the cost of the masks across multiple projects.
So, you must provide them the mask layers, generally as a "Calma stream", and they have to meet a number of criteria to be acceptable for fabrication.
If the mask data is accepted, then MOSIS handles the whole interaction with the fab.
Jon