So, I have a pcb with only blind microvias. The metals on different layers have different thicknesses and as a result each of my micro-vias and metals has different pitch/diameter/spacing.
I 'fixed' this by having a separate clearance rule for each layer. The rule would be something like 'Where first object matches InLayer('M1') and second object matches InLayer('M1')' . This seems to work fine for 99% of my design - but it doest seem to catch a lot of via annular ring clearance issues. Even though my DRC is clean in altium, the manufacturer says there are a lot of DRC errors still remaining. EG the via below, which is too close to the metals on the left and right, clearly violates the DRC rules, yet the DRC results are clean for that metal layer.