Hi,
I need to define a clearance rule that starts from the vias hole edge and not the copper (Annular ring) edge.
For comparison, heres the clearance setup from altium (from copper edge):
And heres the one that i need (from hole edge):
Reason is, on the inner layers i removed the non-functional-pads (so no annular ring).
Now if i set a normal clearance rule for vias i can only define one clearance for all layers (because vias are in Multi-Layer).
If i set the clearance for the viahole to copper (from pcb manufacturer) on the inner-Layer if theres no annular-ring its fine, but if theres an annular-ring its way to big because the rule starts at the copper edge.
Here an example, the rule from the manufacturer says that the clearance from the hole-edge to copper has to be at least 150um.
In the picture you can see that GND via with no annular Ring is fine, but the CS Via with ring isnt because the rule starts at the rings edge.
I couldnt find any query command that would fit my problem.
I hope someone can help me.