Thanks,
NetClass_A to NetClass_A clearance?
Hi, if you have a NetClass_A and you want its nets to be minimum of 3mm clearanced from each other, can you do that in a Clearance Design Rule?........i wondered if it could be difficult, because Altium may try and make the nets clearanced from themselves!?......like.....Net_A must be 0.3mm away from Net_A........Doh!....obviously i wouldnt want that.
How to have keepout under SMD component so that copper pour does not go under it?
Please advise?
How to have a courtyard round a component, such that when you push to opposite layer, courtyard goes with it?
Please advise?
Change all circular vias of 0.8D/0.5Hole to 0.6D/0.3hole
.....Do you know how to do this?
How to do auto-routing
Hi, i have been given a board to gerber up. However, its 4 layer, and the ground plane is so badly cut up that it needs re-doing. Its a micro with loads of connections to lots of opamps, etc, over the board. I believe i will first put in the layer 1 and layer 2 ground planes....then add ground stitching vias near the chips...then autoroute from there. Is it possible to identify a load of circuitry, and then select it, and then just hit "autoroute, and then it all just happens? Noting that first you have to identify your "preferred" track width for each net, and give the clearance of each net from each other.
Also, we wish the autorouting to be done without going inbetween the pads of an IC or component. (ie no tracks going underneath component bodies)
How to define all vias on PCB as being tented?
...Please advise how?
How to locate all vias of drill diameter 0.6mm?
I can get the "shape" thing that corresponds to them in the drill table...but still finding all 26 of the 0.6mm diameter vias is not easy...do you know a quick way?
Repour shelved vias?
Hi, can you repour vias that are shelved....?....i always get , "repour vias because DRC needs it"....but do i have to then unshelve them, then repour them?...then shelve them again because you cant correct DRC errors with the pours poured.
Component pushing
Hi,
When i am solving clearance errors by pushing components about, sometimes the next adjacent component starts getting pushed away, before the component that i am moving has got near to it.......there is no collision, but the other component moves away...which is not wanted. How do i stop this? I mean, i have the pusher on...but i dont expect components to get moved before i get near to them. I turned off silk to silk clearance in design rules, but it made no difference.
Vias changed to have 0mm solder mask expansion causes problem
I just made a design rule to make all vias have 0mm solder mask expansion....and Altium must have moved some of the vias nearer to pads, because i am getting minimum solder mask sliver errors which i never got before. Is this a bug in altium.?
Slots in PCB in mechanical layer?
Hi, I put some slots in my PCB using the Altium "SLOT
Change all track widths on PCB?
Hi, just routed a PCB....used many 0.2mm traces....now realise 2oz copper cannot be done with 0.2mm traces without much expense...so now, how do i convert all the 0.2mm traces to 0.25mm traces?
Wont allow error tracks to be moved?
Hi, I have just changed the thickness of all 0.2mm thick traces on layer 2 to be 0.25mm instead. So now there are clearance issues where the tracks are too near to each other.....sometimes it lets me move the track to solve the clearance, but very often it wont let me move it....why wont it let me move it?
Its not as if i am trying to move it into a clearance problem place.
I am speaking of the bits of tracks that are now coloured green as they are clearance error tracks.
...................OK...now it has let me move them.....i just tried moving them from different points, and eventually it let me move them..why is this?