DDR memory bit width questions

[Jenny]

Hi guys.

According to https://en.wikipedia.org/wiki/Memory_bandwidth#Bandwidth_computation_and_nomenclature, “Each DDR, DDR2, or DDR3 memory interface is 64 bits wide.” But in https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip, those processors are using all kinds of different bus width per channel, such as 32 or 16 bits.

Q1. Why and how they don’t use the standard bus bit width? I recall all x86 system should have 64 bit per channel, are ARM systems just different?
Q2. What’s the difference between two system with same total bit width, but different channel count(such as 4 channels x 16 bit each VS single channel 64 bit)?

Thanks.

[magic]

Just Wikipedia being full of it as usual. Most of it is written by children who just learned something new and need to share it with the world

RAM modules made for x86 systems are always 64 bit wide because that's what the x86 needs.
RAM chips are available in bit widths like 8 or 16 and it takes a few side by side to assemble a module that x86 would be happy with.
Other CPUs may use other widths. If you take apart some embedded system (router, digital camera, ...) it's not unusual to see a SoC being happy with just one RAM chip.

Q2: the channels are independent and can be doing different things at the same time.

[David Hess]

According to https://en.wikipedia.org/wiki/Memory_bandwidth#Bandwidth_computation_and_nomenclature, “Each DDR, DDR2, or DDR3 memory interface is 64 bits wide.” But in https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip, those processors are using all kinds of different bus width per channel, such as 32 or 16 bits.

The Wikipedia article is referring to the width of standard DDR, DDR2, and DDR3 DIMMs.

Q1. Why and how they don’t use the standard bus bit width? I recall all x86 system should have 64 bit per channel, are ARM systems just different?

x86 systems did not always use 64 bit wide memory channels and some support wider memory channels; SIMMs were commonly 8 and then 32 bits wide.  64 bits is a convenient minimum width because it is the smallest width where parity and ECC take the same number of additional bits.

Q2. What’s the difference between two system with same total bit width, but different channel count(such as 4 channels x 16 bit each VS single channel 64 bit)?

Each channel can be accessed independently of the others increasing parallelism.

[magic]

To elaborate on Q2, it's a difference in how you wire the control pins and how the RAM controller works.

Multiple chips making up a wider module: all chips receive the same commands, the data bus is split between them.
Multiple chips on multiple channels: each channel receives its own commands separately and has its own data bus independently scheduled by the controller.

Total bus width and peak throughput adds up to the same number in either case.

See also: ganged vs unganged dual channel mode on x86.

[David Hess]

See also: ganged vs unganged dual channel mode on x86.

Just to elaborate, ganged channels are sent the same command and address data so they operate as one wider channel.  This may be desired for simplicity or lower the drive requirements on the address and control lines.

[Jenny]

Thank you everyone!