Memory ordering at this point is left to implementation, the ISA just providing fence instructions. Not unreasonable. Possibly a bit slippery, or unsufficiently fine-grained.
Not quite knowing all the details of memory ordering has caused huge issues with other instruction sets. That has been partly due to the ordering logic changing over time, and partly that corner cases have not always been thoroughly documented in clear unambiguous language.
That is indeed true.
And that is why FORMALLY defining memory ordering semantics was one of the FIRST things RISC-V did, seven years ago, before anyone even had any multi-core RISC-V processors.
See my previous message.
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