Microcontroller simulation using Xilinx FPGA

[scarletpimpernel]

Boys and girls,

Looking for some input and ideas here ..

The proposition is to be able to simulate different microcontrollers and architectures thereof using Xilinx FPGA devices.  Thoughts along the lines of using published VHDL models of target devices to generate FPGA code;  Where these are not available, then use target's design and dev tools to generate VIDL models that will go into code production.

The aim: to be able to reconfigure a Xilinx FPGA in such a was as to run binary image code from various microcontrollers.


What's your thoughts? anyone went down this line before? anyone interested in hooking up to do that?

[Balaur]

That's called hardware emulation and it's done extensively in both academic and industrial fields.

[slateraptor]

Synthesized an architecture almost identical to the Motorola HC11 less interrupt capability as a final project in digital design. Currently working on a project that incorporates a sketch 6502 core (T65 project from opencores.org) on a custom Cyclone IV platform (with a complete hardware redesign around a Spartan-6 circa summer next year).

If you've never done it before, you'll have your work cut out for you even if it were to synthesize a relatively simple 8-bit von Neumann architecture.

[scarletpimpernel]

Thanks for your response everyone.

I'm mostly interested in Freescale and Infinion devices. I agree it's a lot of work but worth the effort, IMHO.  The intended application is to to construct a generic configurable hardware platform that can emulate the intended target processors, to be able to debug already integrated applications in situ.

So the next question, I guess is whether anyone is interested to form a working team around this and get some traction behind the effort by starting with the lower-end devices (e.g. HC05, HC08, HC11 ...etc), then moving up the ladder towards the more powerful variants.

Thought: we could start with pre-existing VHDL models from vendors, and put Cadence, Mentor Graphics and other such tools to good use?.
Thought: get a wiki behind this.

Any volunteers? 

[joelby]

Can you describe in a bit more detail what you want to do?

There are open source implementations of HC11, AVRs, PICs, etc. but these are just 'clean room' implementations and may not be cycle accurate, or might contain new/different bugs to the silicon, so debugging an application that would eventually call for a 'real' processor using a third-party model would be ill-advised. Manufacturers generally don't release HDL for their own devices for obvious reasons. Have you actually found official models? OpenSPARC is the only one that comes to mind.

If you just want to use your PIC/AVR/whatever compiler or development environment to produce programs for FPGA soft cores, you should already be able to do this with a decent core implementation.

Most modern microcontrollers contain in-circuit debugging interfaces, so in-circuit emulation seems to be a thing of the past. A generic hardware platform that can emulate many different processors in situ would be tricky, since chips come in so many different packages and sockets are hardly used these days. How would you emulate integrated analog peripherals such as an ADC?

[Balaur]

Thanks for your response everyone.

I'm mostly interested in Freescale and Infinion devices. I agree it's a lot of work but worth the effort, IMHO. 

I frankly fail to see the interest and what could be gained from such endeavor.
There are legitimate uses for hardware emulation such as ASIC design, fault simulations and so on. It looks to me that this is not one of these cases.

As a general rule, if a device is commercially available, it's much more practical to build a (prototyping, development, validation, whatever) system/board around the IC.

The intended application is to to construct a generic configurable hardware platform that can emulate the intended target processors, to be able to debug already integrated applications in situ.

Again, without even mentioning very challenging aspects on the hardware and software side, why this approach could be useful?

So the next question, I guess is whether anyone is interested to form a working team around this and get some traction behind the effort by starting with the lower-end devices (e.g. HC05, HC08, HC11 ...etc), then moving up the ladder towards the more powerful variants.

Do you suggest to spend all this effort on several iterations? This is highly inefficient.

Thought: we could start with pre-existing VHDL models from vendors, and put Cadence, Mentor Graphics and other such tools to good use?.

Are you talking about structural or functional HDL models from vendors?
(Please be aware that VHDL is a hardware description language (HDL), like Verilog as well, and it's more appropriate to use the HDL term)

A structural model allows you to actually synthesize the device to a specific target (such as FPGAs, technological processes and so on). It is what you would need in the context of your proposal.

A functional model allows you to simulate the device in order to be able to develop, simulate and validate a complete system including the IP block from the vendor.

It is very unlikely to obtain a structural model from anybody.  If you are talking about commercially available devices (in an IC form), then it makes no sense for a chip provider to give you that. Even for ARM cores that are intended to be integrated in SoCs, most of the time you will not see or need the actual structural information. The foundry will fill the black box with the appropriate structures.

You may get a functional model, but it's not easily usable in your project.

Of course, you can also use publicly available blocks from Open Cores. That's good for training purposes, but you are not guaranteed to have a clock-cycle-perfect emulation of the Device Under Test. Thus, again it makes no sense.

Any volunteers? 

Kids these days... 

[scarletpimpernel]

Thanks for your response everyone.

I'm mostly interested in Freescale and Infinion devices. I agree it's a lot of work but worth the effort, IMHO. 

I frankly fail to see the interest and what could be gained from such endeavor.
There are legitimate uses for hardware emulation such as ASIC design, fault simulations and so on. It looks to me that this is not one of these cases.

Don't be so quick to judge, I've not even discussed what the end "endeavour" is.

As a general rule, if a device is commercially available, it's much more practical to build a (prototyping, development, validation, whatever) system/board around the IC.

Ditto, above comment.

The intended application is to to construct a generic configurable hardware platform that can emulate the intended target processors, to be able to debug already integrated applications in situ.

Again, without even mentioning very challenging aspects on the hardware and software side, why this approach could be useful?

Now you're asking a useful question.  The end result of the intended system is to be able to quickly reconfigure the platform for different processors/series ...etc. without the need for building expensive personality modules or prototyping hardware.

So the next question, I guess is whether anyone is interested to form a working team around this and get some traction behind the effort by starting with the lower-end devices (e.g. HC05, HC08, HC11 ...etc), then moving up the ladder towards the more powerful variants.

Do you suggest to spend all this effort on several iterations? This is highly inefficient.

That's one possibility, reusing as much available VHDL along the line as possible.  I can argue efficiency with you as much as you wish, down to project management methodologies, though that's not the spirit nor intended goal of the post.

Thought: we could start with pre-existing VHDL models from vendors, and put Cadence, Mentor Graphics and other such tools to good use?.

Are you talking about structural or functional HDL models from vendors?
(Please be aware that VHDL is a hardware description language (HDL), like Verilog as well, and it's more appropriate to use the HDL term)

A structural model allows you to actually synthesize the device to a specific target (such as FPGAs, technological processes and so on). It is what you would need in the context of your proposal.

A functional model allows you to simulate the device in order to be able to develop, simulate and validate a complete system including the IP block from the vendor.

It is very unlikely to obtain a structural model from anybody.  If you are talking about commercially available devices (in an IC form), then it makes no sense for a chip provider to give you that. Even for ARM cores that are intended to be integrated in SoCs, most of the time you will not see or need the actual structural information. The foundry will fill the black box with the appropriate structures.

You may get a functional model, but it's not easily usable in your project.

Of course, you can also use publicly available blocks from Open Cores. That's good for training purposes, but you are not guaranteed to have a clock-cycle-perfect emulation of the Device Under Test. Thus, again it makes no sense.

Thanks for the 1st year undergrad intro material; again, sparking an argument is not the intended target.  I am referring to Functional HDL, and I do mean VHDL, given the tools in mind (Mentor ...etc) and the Xilinx platform.

Any volunteers? 

Kids these days... 

I won't even respond to this, it's so petty.